| Message ID | 20211207092909.2933-1-damien.hedde@greensocs.com |
|---|---|
| State | New |
| Headers | show |
| Series | | expand |
Sorry for the inconvenience, I screwed-up with the subject line. Should I resend ? Damien On 12/7/21 10:29, Damien Hedde wrote: > Subject: [PATCH for 6.2?] gicv3: fix ICH_MISR's LRENP computation > > According to the "Arm Generic Interrupt Controller Architecture > Specification GIC architecture version 3 and 4" (version G: page 345 > for aarch64 or 509 for aarch32): > LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and > ICH_HCR.EOIcount is non-zero. > > When only LRENPIE was set (and EOI count was zero), the LRENP bit was > wrongly set and MISR value was wrong. > > As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, > the maintenance interrupt was constantly fired. It happens since patch > 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") > which fixed another bug about maintenance interrupt (most significant > bits of misr, including this one, were ignored in the interrupt trigger). > > Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers") > Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> > --- > The gic doc is available here: > https://developer.arm.com/documentation/ihi0069/g > --- > hw/intc/arm_gicv3_cpuif.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c > index 7fba931450..85fc369e55 100644 > --- a/hw/intc/arm_gicv3_cpuif.c > +++ b/hw/intc/arm_gicv3_cpuif.c > @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) > /* Scan list registers and fill in the U, NP and EOI bits */ > eoi_maintenance_interrupt_state(cs, &value); > > - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { > + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && > + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { > value |= ICH_MISR_EL2_LRENP; > } > >
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fba931450..85fc369e55 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) /* Scan list registers and fill in the U, NP and EOI bits */ eoi_maintenance_interrupt_state(cs, &value); - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { value |= ICH_MISR_EL2_LRENP; }
Subject: [PATCH for 6.2?] gicv3: fix ICH_MISR's LRENP computation According to the "Arm Generic Interrupt Controller Architecture Specification GIC architecture version 3 and 4" (version G: page 345 for aarch64 or 509 for aarch32): LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and ICH_HCR.EOIcount is non-zero. When only LRENPIE was set (and EOI count was zero), the LRENP bit was wrongly set and MISR value was wrong. As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, the maintenance interrupt was constantly fired. It happens since patch 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") which fixed another bug about maintenance interrupt (most significant bits of misr, including this one, were ignored in the interrupt trigger). Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers") Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> --- The gic doc is available here: https://developer.arm.com/documentation/ihi0069/g --- hw/intc/arm_gicv3_cpuif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)