@@ -128,6 +128,9 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
@@ -1370,6 +1370,21 @@ static void pnv_chip_power9_instance_init(Object *obj)
chip->num_phbs = pcc->num_phbs;
}
+static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
+ PnvCore *pnv_core)
+{
+ char eq_name[32];
+ int core_id = CPU_CORE(pnv_core)->core_id;
+
+ snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
+ object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
+ sizeof(*eq), TYPE_PNV_QUAD,
+ &error_fatal, NULL);
+
+ object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
+ qdev_realize(DEVICE(eq), NULL, &error_fatal);
+}
+
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
@@ -1379,18 +1394,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
for (i = 0; i < chip9->nr_quads; i++) {
- char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = chip->cores[i * 4];
- int core_id = CPU_CORE(pnv_core)->core_id;
-
- snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
- object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
- &error_fatal, NULL);
- object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
- qdev_realize(DEVICE(eq), NULL, &error_fatal);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1606,6 +1612,24 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
}
+static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(chip10);
+ int i;
+
+ chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
+ chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
+
+ for (i = 0; i < chip10->nr_quads; i++) {
+ PnvQuad *eq = &chip10->quads[i];
+
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
+ &eq->xscom_regs);
+ }
+}
+
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -1627,6 +1651,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
return;
}
+ pnv_chip_power10_quad_realize(chip10, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* XIVE2 interrupt controller (POWER10) */
object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
PNV10_XIVE2_IC_BASE(chip), &error_fatal);
and use a pnv_chip_power10_quad_realize() helper to avoid code duplication with P9. This still needs some refinements on the XSCOM registers handling in PnvQuad. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv.h | 3 +++ hw/ppc/pnv.c | 50 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 43 insertions(+), 10 deletions(-)