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[v5,08/22] target/riscv: Relax debug check for pm write

Message ID 20211125073951.57678-9-zhiwei_liu@c-sky.com
State New
Headers show
Series Support UXL filed in xstatus | expand

Commit Message

LIU Zhiwei Nov. 25, 2021, 7:39 a.m. UTC 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4ee897be2..bfafd3bd96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1465,6 +1465,9 @@  static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
     int csr_priv = get_field(csrno, 0x300);
     int pm_current;
 
+    if (env->debugger) {
+        return false;
+    }
     /*
      * If priv lvls differ that means we're accessing csr from higher priv lvl,
      * so allow the access