| Message ID | 20211028210843.2120802-21-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Fully convert MSA opcodes to decodetree | expand |
On 10/28/21 2:08 PM, Philippe Mathieu-Daudé wrote: > +@3r ...... ... df:2 wt:5ws:5 wd:5 ...... &msa_r Nit: should this be called @3rf, since it includes df and... > +TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); ... you use trans_msa_3rf as the implementation? r~
On 10/29/21 18:35, Richard Henderson wrote: > On 10/28/21 2:08 PM, Philippe Mathieu-Daudé wrote: >> +@3r ...... ... df:2 wt:5ws:5 wd:5 ...... &msa_r > > Nit: should this be called @3rf, since it includes df and... "3R" is how the manual names this instruction class: Figure 3-40 3R Instruction Format 3R has 2-bit DF field, 3RF has 1-bit DF field. The other arguments are the same (for the helpers). >> +TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); > > ... you use trans_msa_3rf as the implementation? Maybe I should name it trans_msa_3r_or_3rf()? Hmm @3r is actually @3r_df_b (DF=0, DF_BYTE). So trans_msa_3rf() is a good name for it. I could rename @3r -> @3r_df_b but then it doesn't match the manual '3R'. All @3r* use &msa_r structure.
On 10/29/21 10:23 AM, Philippe Mathieu-Daudé wrote: > On 10/29/21 18:35, Richard Henderson wrote: >> On 10/28/21 2:08 PM, Philippe Mathieu-Daudé wrote: >>> +@3r ...... ... df:2 wt:5ws:5 wd:5 ...... &msa_r >> >> Nit: should this be called @3rf, since it includes df and... > > "3R" is how the manual names this instruction class: > > Figure 3-40 3R Instruction Format > > 3R has 2-bit DF field, 3RF has 1-bit DF field. The other > arguments are the same (for the helpers). Ok, I see. r~
On 10/29/21 19:50, Richard Henderson wrote: > On 10/29/21 10:23 AM, Philippe Mathieu-Daudé wrote: >> On 10/29/21 18:35, Richard Henderson wrote: >>> On 10/28/21 2:08 PM, Philippe Mathieu-Daudé wrote: >>>> +@3r ...... ... df:2 wt:5ws:5 wd:5 ...... &msa_r >>> >>> Nit: should this be called @3rf, since it includes df and... >> >> "3R" is how the manual names this instruction class: >> >> Figure 3-40 3R Instruction Format >> >> 3R has 2-bit DF field, 3RF has 1-bit DF field. The other >> arguments are the same (for the helpers). > > Ok, I see. FYI I amended: Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field. to the commit description.
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 1d6ada4c142..4b14acce26f 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -32,6 +32,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w +@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h @3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -88,6 +89,11 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + SLD 011110 000 .. ..... ..... ..... 010100 @3r + SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + + VSHF 011110 000 .. ..... ..... ..... 010101 @3r + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index fbaf9f622f3..6738a2b8cd7 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -58,15 +58,12 @@ enum { OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12, OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15, OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12, OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14, OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E, @@ -503,6 +500,11 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); +TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); +TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); + +TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1253,12 +1255,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBV_df: switch (df) { case DF_BYTE: @@ -1291,9 +1287,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: switch (df) { case DF_BYTE: