| Message ID | 20211022174550.36937-4-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: MSA opcode fixes | expand |
On 10/22/21 19:45, Philippe Mathieu-Daudé wrote: > When using the Loongson-3A4000 CPU, the MSAIR is returned with a > zero value (because unimplemented). Checking on real hardware, > this value appears incorrect: > > $ cat /proc/cpuinfo > system type : generic-loongson-machine > machine : loongson,generic > cpu model : Loongson-3 V0.4 FPU V0.1 > model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz > isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 > ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 > ... > > Checking the CFCMSA opcode result with gdb we get 0x60140: > > Breakpoint 1, 0x00000001200037c4 in main () > 1: x/i $pc > => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir > (gdb) si > 0x00000001200037c8 in main () > (gdb) i r v0 > v0: 0x60140 > > So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in > commit af868995e1b ("target/mips: Add Loongson-3 CPU definition"). > > Cc: Huacai Chen <chenhuacai@kernel.org> > Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/mips/cpu-defs.c.inc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index cbc45fcb0e8..f43a8e7c9d9 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] = > (0x1 << FCR0_D) | (0x1 << FCR0_S), > .CP1_fcr31 = 0, > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > + .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), Rev and ProcID are 8-bit, then only bit 16 is defined in the spec (WRP: Vector Registers Partitioning). Bits 17 and 18 are "reserved" per the spec revision 1.12. Changing that by .MSAIR = (1 << MSAIR_ProcID), or .MSAIR = (1 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), allows guests to see non-zero Implementation ProcessorID.
在 2021/10/22 18:45, Philippe Mathieu-Daudé 写道: > When using the Loongson-3A4000 CPU, the MSAIR is returned with a > zero value (because unimplemented). Checking on real hardware, > this value appears incorrect: > > $ cat /proc/cpuinfo > system type : generic-loongson-machine > machine : loongson,generic > cpu model : Loongson-3 V0.4 FPU V0.1 > model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz > isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 > ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 > ... > > Checking the CFCMSA opcode result with gdb we get 0x60140: > > Breakpoint 1, 0x00000001200037c4 in main () > 1: x/i $pc > => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir > (gdb) si > 0x00000001200037c8 in main () > (gdb) i r v0 > v0: 0x60140 > > So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in > commit af868995e1b ("target/mips: Add Loongson-3 CPU definition"). > > Cc: Huacai Chen <chenhuacai@kernel.org> > Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > target/mips/cpu-defs.c.inc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index cbc45fcb0e8..f43a8e7c9d9 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] = > (0x1 << FCR0_D) | (0x1 << FCR0_S), > .CP1_fcr31 = 0, > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > + .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), > .SEGBITS = 48, > .PABITS = 48, > .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index cbc45fcb0e8..f43a8e7c9d9 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] = (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 = 0, .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .MSAIR = (0x601 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 So set MSAIR=0x60140 for the Loongson-3A4000 CPU model added in commit af868995e1b ("target/mips: Add Loongson-3 CPU definition"). Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 1 + 1 file changed, 1 insertion(+)