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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id d16sm13728474wmb.2.2021.10.03.10.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Oct 2021 10:58:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 7/8] target/mips: Use tcg_constant_i32() in gen_msa_i5() Date: Sun, 3 Oct 2021 19:57:42 +0200 Message-Id: <20211003175743.3738710-8-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211003175743.3738710-1-f4bug@amsat.org> References: <20211003175743.3738710-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa_translate.c | 40 ++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 3ef912da6b8..3ede2f643c0 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -473,14 +473,32 @@ static void gen_msa_i8(DisasContext *ctx) static void gen_msa_i5(DisasContext *ctx) { #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 = extract32(ctx->opcode, 16, 5); - TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2)); TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5)); TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5)); - TCGv_i32 timm = tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); + TCGv_i32 timm; + + switch (MASK_MSA_I5(ctx->opcode)) { + case OPC_ADDVI_df: + case OPC_MAXI_U_df: + case OPC_MINI_U_df: + case OPC_CLTI_U_df: + case OPC_CLEI_U_df: + timm = tcg_constant_i32(extract32(ctx->opcode, 16, 5)); + break; + case OPC_MAXI_S_df: + case OPC_MINI_S_df: + case OPC_CEQI_df: + case OPC_CLTI_S_df: + case OPC_CLEI_S_df: + timm = tcg_constant_i32(sextract32(ctx->opcode, 16, 5)); + break; + case OPC_LDI_df: + timm = tcg_constant_i32(sextract32(ctx->opcode, 11, 10)); + break; + default: + break; + } switch (MASK_MSA_I5(ctx->opcode)) { case OPC_ADDVI_df: @@ -490,43 +508,34 @@ static void gen_msa_i5(DisasContext *ctx) gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); break; case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); break; case OPC_MAXI_U_df: gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); break; case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); break; case OPC_MINI_U_df: gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); break; case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); break; case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); break; case OPC_CLTI_U_df: gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); break; case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); break; case OPC_CLEI_U_df: gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); break; case OPC_LDI_df: - { - int32_t s10 = sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } + gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); break; default: MIPS_INVAL("MSA instruction"); @@ -537,7 +546,6 @@ static void gen_msa_i5(DisasContext *ctx) tcg_temp_free_i32(tdf); tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); } static void gen_msa_bit(DisasContext *ctx)