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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id f8sm14727277wrx.15.2021.09.26.15.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Sep 2021 15:28:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v8 13/40] accel/tcg: Implement AccelOpsClass::has_work() Date: Mon, 27 Sep 2021 00:26:49 +0200 Message-Id: <20210926222716.1732932-14-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210926222716.1732932-1-f4bug@amsat.org> References: <20210926222716.1732932-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All accelerators but TCG implement their AccelOpsClass::has_work() handler, meaning all the remaining CPUClass::has_work() ones are only reachable from TCG accelerator; and these has_work() handlers belong to TCGCPUOps. We will gradually move each target CPUClass::has_work() to TCGCPUOps in the following commits. For now, move the CPUClass::has_work() call to tcg_cpu_has_work(), the TCG AccelOpsClass::has_work() implementation. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- accel/tcg/tcg-accel-ops.c | 11 +++++++++++ softmmu/cpus.c | 5 ----- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e2dd171a13f..114eb3b9b2c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,7 +89,7 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @has_work: Callback for checking if there is work to do. + * @has_work: Callback for checking if there is work to do. Only used by TCG. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @get_arch_id: Callback for getting architecture-dependent CPU ID. diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 1a8e8390bd6..ebaacff1842 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -73,6 +73,16 @@ int tcg_cpus_exec(CPUState *cpu) return ret; } +static bool tcg_cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->has_work) { + return cc->has_work(cpu); + } + return false; +} + /* mask must never be zero, except for A20 change call */ void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -108,6 +118,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) ops->kick_vcpu_thread = rr_kick_vcpu_thread; ops->handle_interrupt = tcg_handle_interrupt; } + ops->has_work = tcg_cpu_has_work; } static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 5ffa02f9cef..bb16a25bcef 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -251,11 +251,6 @@ void cpu_interrupt(CPUState *cpu, int mask) bool cpu_has_work(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->has_work && cc->has_work(cpu)) { - return true; - } if (cpus_accel->has_work && cpus_accel->has_work(cpu)) { return true; }