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[v8,11/40] accel/nvmm: Implement AccelOpsClass::has_work()

Message ID	20210926222716.1732932-12-f4bug@amsat.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PATCH v8 11/40] accel/nvmm: Implement AccelOpsClass::has_work() Date: Mon, 27 Sep 2021 00:26:47 +0200 Message-Id: <20210926222716.1732932-12-f4bug@amsat.org> In-Reply-To: <20210926222716.1732932-1-f4bug@amsat.org> References: <20210926222716.1732932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	accel: Move has_work() from CPUClass to AccelOpsClass \| expand [v8,00/40] accel: Move has_work() from CPUClass to AccelOpsClass [v8,01/40] accel: Simplify qemu_init_vcpu() [v8,02/40] hw/core: Restrict cpu_has_work() to sysemu [v8,03/40] hw/core: Un-inline cpu_has_work() [v8,04/40] hw/core: Move cpu_common_has_work() to cpu_has_work() [v8,05/40] accel: Introduce AccelOpsClass::has_work() [v8,06/40] accel/kvm: Implement AccelOpsClass::has_work() [v8,07/40] accel/whpx: Implement AccelOpsClass::has_work() [v8,08/40] accel/hvf: Implement AccelOpsClass::has_work() [v8,09/40] accel/xen: Implement AccelOpsClass::has_work() [v8,10/40] accel/hax: Implement AccelOpsClass::has_work() [v8,11/40] accel/nvmm: Implement AccelOpsClass::has_work() [v8,12/40] accel/qtest: Implement AccelOpsClass::has_work() [v8,13/40] accel/tcg: Implement AccelOpsClass::has_work() [v8,14/40] accel: Simplify cpu_has_work() [v8,15/40] accel/tcg: Introduce TCGCPUOps::has_work() [v8,16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work [v8,17/40] target/arm: Restrict has_work() handler to sysemu and TCG [v8,18/40] target/alpha: Restrict has_work() handler to sysemu [v8,19/40] target/avr: Restrict has_work() handler to sysemu [v8,20/40] target/cris: Restrict has_work() handler to sysemu [v8,21/40] target/hexagon: Remove unused has_work() handler [v8,22/40] target/hppa: Restrict has_work() handler to sysemu [v8,23/40] target/i386: Restrict has_work() handler to sysemu and TCG [v8,24/40] target/m68k: Restrict has_work() handler to sysemu [v8,25/40] target/microblaze: Restrict has_work() handler to sysemu [v8,26/40] target/mips: Restrict has_work() handler to sysemu and TCG [v8,27/40] target/nios2: Restrict has_work() handler to sysemu [v8,28/40] target/openrisc: Restrict has_work() handler to sysemu [v8,29/40] target/ppc: Introduce PowerPCCPUClass::has_work() [v8,30/40] target/ppc: Restrict has_work() handlers to sysemu and TCG [v8,31/40] target/riscv: Restrict has_work() handler to sysemu and TCG [v8,32/40] target/rx: Restrict has_work() handler to sysemu [v8,33/40] target/s390x: Restrict has_work() handler to sysemu and TCG [v8,34/40] target/sh4: Restrict has_work() handler to sysemu [v8,35/40] target/sparc: Remove pointless use of CONFIG_TCG definition [v8,36/40] target/sparc: Restrict has_work() handler to sysemu [v8,37/40] target/tricore: Restrict has_work() handler to sysemu [v8,38/40] target/xtensa: Restrict has_work() handler to sysemu [v8,39/40] accel/tcg: Remove CPUClass::has_work() [v8,40/40] accel/tcg: Simplify tcg_cpu_has_work()

Commit Message

Philippe Mathieu-Daudé Sept. 26, 2021, 10:26 p.m. UTC

Since there is no specific NVMM handling for cpu_has_work() in
cpu_thread_is_idle(), implement NVMM has_work() handler as a
simple 'return false' code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/i386/nvmm/nvmm-accel-ops.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Richard Henderson Sept. 27, 2021, 12:02 a.m. UTC | #1

On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
> Since there is no specific NVMM handling for cpu_has_work() in
> cpu_thread_is_idle(), implement NVMM has_work() handler as a
> simple 'return false' code.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/i386/nvmm/nvmm-accel-ops.c | 6 ++++++
>   1 file changed, 6 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

diff mbox series

Patch

diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c
index f788f75289f..36296f79ff8 100644
--- a/target/i386/nvmm/nvmm-accel-ops.c
+++ b/target/i386/nvmm/nvmm-accel-ops.c
@@ -83,6 +83,11 @@  static void nvmm_kick_vcpu_thread(CPUState *cpu)
     cpus_kick_thread(cpu);
 }
 
+static bool nvmm_cpu_has_work(CPUState *cpu)
+{
+    return false;
+}
+
 static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data)
 {
     AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
@@ -94,6 +99,7 @@  static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data)
     ops->synchronize_post_init = nvmm_cpu_synchronize_post_init;
     ops->synchronize_state = nvmm_cpu_synchronize_state;
     ops->synchronize_pre_loadvm = nvmm_cpu_synchronize_pre_loadvm;
+    ops->has_work = nvmm_cpu_has_work;
 }
 
 static const TypeInfo nvmm_accel_ops_type = {