| Message ID | 20210909203439.4114179-2-matheus.ferst@eldorado.org.br |
|---|---|
| State | New |
| Headers | show |
| Series | Require hypervisor privilege for tlbie[l] when PSR=0 and HR=1. | expand |
On 9/9/21 5:34 PM, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst <matheus.ferst@eldorado.org.br> > > Add a Host Radix field (hr) in DisasContext with LPCR[HR] value to allow > us to decide between Radix and HPT while validating instructions > arguments. Note that PowerISA v3.1 does not require LPCR[HR] and PATE.HR > to match if the thread is in ultravisor/hypervisor real addressing mode, > so ctx->hr may be invalid if ctx->hv and ctx->dr are set. > > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > target/ppc/cpu.h | 1 + > target/ppc/helper_regs.c | 3 +++ > target/ppc/translate.c | 2 ++ > 3 files changed, 6 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 500205229c..e1b8d343cd 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -600,6 +600,7 @@ enum { > HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ > HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ > HFLAGS_DR = 4, /* MSR_DR */ > + HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */ > HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ > HFLAGS_TM = 8, /* computed from MSR_TM */ > HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ > diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c > index 405450d863..1bfb480ecf 100644 > --- a/target/ppc/helper_regs.c > +++ b/target/ppc/helper_regs.c > @@ -106,6 +106,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) > if (env->spr[SPR_LPCR] & LPCR_GTSE) { > hflags |= 1 << HFLAGS_GTSE; > } > + if (env->spr[SPR_LPCR] & LPCR_HR) { > + hflags |= 1 << HFLAGS_HR; > + } > > #ifndef CONFIG_USER_ONLY > if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 171b216e17..909a092fde 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -175,6 +175,7 @@ struct DisasContext { > bool spe_enabled; > bool tm_enabled; > bool gtse; > + bool hr; > ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ > int singlestep_enabled; > uint32_t flags; > @@ -8539,6 +8540,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; > ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; > ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; > + ctx->hr = (hflags >> HFLAGS_HR) & 1; > > ctx->singlestep_enabled = 0; > if ((hflags >> HFLAGS_SE) & 1) { >
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 500205229c..e1b8d343cd 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -600,6 +600,7 @@ enum { HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ HFLAGS_DR = 4, /* MSR_DR */ + HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 405450d863..1bfb480ecf 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -106,6 +106,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (env->spr[SPR_LPCR] & LPCR_GTSE) { hflags |= 1 << HFLAGS_GTSE; } + if (env->spr[SPR_LPCR] & LPCR_HR) { + hflags |= 1 << HFLAGS_HR; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..909a092fde 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -175,6 +175,7 @@ struct DisasContext { bool spe_enabled; bool tm_enabled; bool gtse; + bool hr; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -8539,6 +8540,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; + ctx->hr = (hflags >> HFLAGS_HR) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) {