diff mbox series

[14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu

Message ID 20210902151715.383678-15-f4bug@amsat.org
State New
Headers show
Series accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu | expand

Commit Message

Philippe Mathieu-Daudé Sept. 2, 2021, 3:17 p.m. UTC 
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/tcg-internal.h      |  5 +++--
 target/mips/cpu.c                   |  2 +-
 target/mips/tcg/exception.c         | 18 ------------------
 target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++
 target/mips/tcg/user/tlb_helper.c   |  5 -----
 5 files changed, 22 insertions(+), 26 deletions(-)

Comments

Warner Losh Sept. 2, 2021, 8:21 p.m. UTC | #1 
On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:

> Restrict cpu_exec_interrupt() and its callees to sysemu.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tcg/tcg-internal.h      |  5 +++--
>  target/mips/cpu.c                   |  2 +-
>  target/mips/tcg/exception.c         | 18 ------------------
>  target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++
>  target/mips/tcg/user/tlb_helper.c   |  5 -----
>  5 files changed, 22 insertions(+), 26 deletions(-)
>
> Reviewed-by: Warner Losh <imp@bsdimp.com>


> diff --git a/target/mips/tcg/tcg-internal.h
> b/target/mips/tcg/tcg-internal.h
> index 81b14eb219e..c7a77ddccdd 100644
> --- a/target/mips/tcg/tcg-internal.h
> +++ b/target/mips/tcg/tcg-internal.h
> @@ -18,8 +18,6 @@
>  void mips_tcg_init(void);
>
>  void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock
> *tb);
> -void mips_cpu_do_interrupt(CPUState *cpu);
> -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
>  bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>                         MMUAccessType access_type, int mmu_idx,
>                         bool probe, uintptr_t retaddr);
> @@ -41,6 +39,9 @@ static inline void QEMU_NORETURN
> do_raise_exception(CPUMIPSState *env,
>
>  #if !defined(CONFIG_USER_ONLY)
>
> +void mips_cpu_do_interrupt(CPUState *cpu);
> +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
> +
>  void mmu_init(CPUMIPSState *env, const mips_def_t *def);
>
>  void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t
> *pagemask);
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index d426918291a..00e0c55d0e4 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
>  static const struct TCGCPUOps mips_tcg_ops = {
>      .initialize = mips_tcg_init,
>      .synchronize_from_tb = mips_cpu_synchronize_from_tb,
> -    .cpu_exec_interrupt = mips_cpu_exec_interrupt,
>      .tlb_fill = mips_cpu_tlb_fill,
>
>  #if !defined(CONFIG_USER_ONLY)
> +    .cpu_exec_interrupt = mips_cpu_exec_interrupt,
>      .do_interrupt = mips_cpu_do_interrupt,
>      .do_transaction_failed = mips_cpu_do_transaction_failed,
>      .do_unaligned_access = mips_cpu_do_unaligned_access,
> diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
> index 4fb8b00711d..7b3026b105b 100644
> --- a/target/mips/tcg/exception.c
> +++ b/target/mips/tcg/exception.c
> @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const
> TranslationBlock *tb)
>      env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
>  }
>
> -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> -{
> -    if (interrupt_request & CPU_INTERRUPT_HARD) {
> -        MIPSCPU *cpu = MIPS_CPU(cs);
> -        CPUMIPSState *env = &cpu->env;
> -
> -        if (cpu_mips_hw_interrupts_enabled(env) &&
> -            cpu_mips_hw_interrupts_pending(env)) {
> -            /* Raise it */
> -            cs->exception_index = EXCP_EXT_INTERRUPT;
> -            env->error_code = 0;
> -            mips_cpu_do_interrupt(cs);
> -            return true;
> -        }
> -    }
> -    return false;
> -}
> -
>  static const char * const excp_names[EXCP_LAST + 1] = {
>      [EXCP_RESET] = "reset",
>      [EXCP_SRESET] = "soft reset",
> diff --git a/target/mips/tcg/sysemu/tlb_helper.c
> b/target/mips/tcg/sysemu/tlb_helper.c
> index a150a014ec1..73254d19298 100644
> --- a/target/mips/tcg/sysemu/tlb_helper.c
> +++ b/target/mips/tcg/sysemu/tlb_helper.c
> @@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs)
>      cs->exception_index = EXCP_NONE;
>  }
>
> +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> +{
> +    if (interrupt_request & CPU_INTERRUPT_HARD) {
> +        MIPSCPU *cpu = MIPS_CPU(cs);
> +        CPUMIPSState *env = &cpu->env;
> +
> +        if (cpu_mips_hw_interrupts_enabled(env) &&
> +            cpu_mips_hw_interrupts_pending(env)) {
> +            /* Raise it */
> +            cs->exception_index = EXCP_EXT_INTERRUPT;
> +            env->error_code = 0;
> +            mips_cpu_do_interrupt(cs);
> +            return true;
> +        }
> +    }
> +    return false;
> +}
> +
>  void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
>  {
>      CPUState *cs = env_cpu(env);
> diff --git a/target/mips/tcg/user/tlb_helper.c
> b/target/mips/tcg/user/tlb_helper.c
> index b835144b820..210c6d529ef 100644
> --- a/target/mips/tcg/user/tlb_helper.c
> +++ b/target/mips/tcg/user/tlb_helper.c
> @@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
>      raise_mmu_exception(env, address, access_type);
>      do_raise_exception_err(env, cs->exception_index, env->error_code,
> retaddr);
>  }
> -
> -void mips_cpu_do_interrupt(CPUState *cs)
> -{
> -    cs->exception_index = EXCP_NONE;
> -}
> --
> 2.31.1
>
>
Richard Henderson Sept. 3, 2021, 7:17 p.m. UTC | #2 
On 9/2/21 5:17 PM, Philippe Mathieu-Daudé wrote:
> Restrict cpu_exec_interrupt() and its callees to sysemu.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/tcg-internal.h      |  5 +++--
>   target/mips/cpu.c                   |  2 +-
>   target/mips/tcg/exception.c         | 18 ------------------
>   target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++
>   target/mips/tcg/user/tlb_helper.c   |  5 -----
>   5 files changed, 22 insertions(+), 26 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 81b14eb219e..c7a77ddccdd 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -18,8 +18,6 @@ 
 void mips_tcg_init(void);
 
 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-void mips_cpu_do_interrupt(CPUState *cpu);
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
                        bool probe, uintptr_t retaddr);
@@ -41,6 +39,9 @@  static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 
 #if !defined(CONFIG_USER_ONLY)
 
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d426918291a..00e0c55d0e4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -539,10 +539,10 @@  static const struct SysemuCPUOps mips_sysemu_ops = {
 static const struct TCGCPUOps mips_tcg_ops = {
     .initialize = mips_tcg_init,
     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
-    .cpu_exec_interrupt = mips_cpu_exec_interrupt,
     .tlb_fill = mips_cpu_tlb_fill,
 
 #if !defined(CONFIG_USER_ONLY)
+    .cpu_exec_interrupt = mips_cpu_exec_interrupt,
     .do_interrupt = mips_cpu_do_interrupt,
     .do_transaction_failed = mips_cpu_do_transaction_failed,
     .do_unaligned_access = mips_cpu_do_unaligned_access,
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index 4fb8b00711d..7b3026b105b 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -86,24 +86,6 @@  void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 }
 
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
-    if (interrupt_request & CPU_INTERRUPT_HARD) {
-        MIPSCPU *cpu = MIPS_CPU(cs);
-        CPUMIPSState *env = &cpu->env;
-
-        if (cpu_mips_hw_interrupts_enabled(env) &&
-            cpu_mips_hw_interrupts_pending(env)) {
-            /* Raise it */
-            cs->exception_index = EXCP_EXT_INTERRUPT;
-            env->error_code = 0;
-            mips_cpu_do_interrupt(cs);
-            return true;
-        }
-    }
-    return false;
-}
-
 static const char * const excp_names[EXCP_LAST + 1] = {
     [EXCP_RESET] = "reset",
     [EXCP_SRESET] = "soft reset",
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index a150a014ec1..73254d19298 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -1339,6 +1339,24 @@  void mips_cpu_do_interrupt(CPUState *cs)
     cs->exception_index = EXCP_NONE;
 }
 
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        MIPSCPU *cpu = MIPS_CPU(cs);
+        CPUMIPSState *env = &cpu->env;
+
+        if (cpu_mips_hw_interrupts_enabled(env) &&
+            cpu_mips_hw_interrupts_pending(env)) {
+            /* Raise it */
+            cs->exception_index = EXCP_EXT_INTERRUPT;
+            env->error_code = 0;
+            mips_cpu_do_interrupt(cs);
+            return true;
+        }
+    }
+    return false;
+}
+
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c
index b835144b820..210c6d529ef 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -57,8 +57,3 @@  bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     raise_mmu_exception(env, address, access_type);
     do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
 }
-
-void mips_cpu_do_interrupt(CPUState *cs)
-{
-    cs->exception_index = EXCP_NONE;
-}