| Message ID | 20210730070742.9674-1-laramglazier@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] target/i386: Added VGIF feature | expand |
On 30/07/21 09:07, Lara Lazier wrote: > v2->v3: moved guest check into virtual_gif_enabled > > VGIF allows STGI and CLGI to execute in guest mode and control virtual > interrupts in guest mode. > When the VGIF feature is enabled then: > * executing STGI in the guest sets bit 9 of the VMCB offset 60h. > * executing CLGI in the guest clears bit 9 of the VMCB offset 60h. > > Signed-off-by: Lara Lazier <laramglazier@gmail.com> This part looks good, I queued it for QEMU 6.2. However, I am wondering if STGI/CLGI should also affect the emulation of VIRQ. I am not very familiar with this part of VGIF because KVM does not need it, but it makes sense that STGI/CLGI respectively unmask and mask VIRQ just like STI/CLI do. Can you look up in the manual if there's anything like this? We can discuss the implementation tomorrow. Thanks, Paolo > --- > target/i386/cpu.c | 3 ++- > target/i386/svm.h | 6 ++++++ > target/i386/tcg/sysemu/svm_helper.c | 31 +++++++++++++++++++++++++++-- > 3 files changed, 37 insertions(+), 3 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index edb97ebbbe..71d26cf1bd 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -631,7 +631,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, > #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ > CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) > #define TCG_EXT4_FEATURES 0 > -#define TCG_SVM_FEATURES CPUID_SVM_NPT > +#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ > + CPUID_SVM_SVME_ADDR_CHK) > #define TCG_KVM_FEATURES 0 > #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ > CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ > diff --git a/target/i386/svm.h b/target/i386/svm.h > index adc058dc76..036597a2ff 100644 > --- a/target/i386/svm.h > +++ b/target/i386/svm.h > @@ -9,6 +9,12 @@ > #define V_IRQ_SHIFT 8 > #define V_IRQ_MASK (1 << V_IRQ_SHIFT) > > +#define V_GIF_ENABLED_SHIFT 25 > +#define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT) > + > +#define V_GIF_SHIFT 9 > +#define V_GIF_MASK (1 << V_GIF_SHIFT) > + > #define V_INTR_PRIO_SHIFT 16 > #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) > > diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c > index 90a9de30f8..b6ad425cca 100644 > --- a/target/i386/tcg/sysemu/svm_helper.c > +++ b/target/i386/tcg/sysemu/svm_helper.c > @@ -110,6 +110,17 @@ static inline bool is_efer_invalid_state (CPUX86State *env) > return false; > } > > +static inline bool virtual_gif_enabled(CPUX86State *env, uint32_t *int_ctl) > +{ > + if (likely(env->hflags & HF_GUEST_MASK)) { > + *int_ctl = x86_ldl_phys(env_cpu(env), > + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); > + return (env->features[FEAT_SVM] & CPUID_SVM_VGIF) > + && (*int_ctl & V_GIF_ENABLED_MASK); > + } > + return false; > +} > + > void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) > { > CPUState *cs = env_cpu(env); > @@ -503,13 +514,29 @@ void helper_vmsave(CPUX86State *env, int aflag) > void helper_stgi(CPUX86State *env) > { > cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0, GETPC()); > - env->hflags2 |= HF2_GIF_MASK; > + > + CPUState *cs = env_cpu(env); > + uint32_t int_ctl; > + if (virtual_gif_enabled(env, &int_ctl)) { > + x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), > + int_ctl | V_GIF_MASK); > + } else { > + env->hflags2 |= HF2_GIF_MASK; > + } > } > > void helper_clgi(CPUX86State *env) > { > cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0, GETPC()); > - env->hflags2 &= ~HF2_GIF_MASK; > + > + CPUState *cs = env_cpu(env); > + uint32_t int_ctl; > + if (virtual_gif_enabled(env, &int_ctl)) { > + x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), > + int_ctl & ~V_GIF_MASK); > + } else { > + env->hflags2 &= ~HF2_GIF_MASK; > + } > } > > bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type) >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index edb97ebbbe..71d26cf1bd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -631,7 +631,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) #define TCG_EXT4_FEATURES 0 -#define TCG_SVM_FEATURES CPUID_SVM_NPT +#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ + CPUID_SVM_SVME_ADDR_CHK) #define TCG_KVM_FEATURES 0 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ diff --git a/target/i386/svm.h b/target/i386/svm.h index adc058dc76..036597a2ff 100644 --- a/target/i386/svm.h +++ b/target/i386/svm.h @@ -9,6 +9,12 @@ #define V_IRQ_SHIFT 8 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) +#define V_GIF_ENABLED_SHIFT 25 +#define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT) + +#define V_GIF_SHIFT 9 +#define V_GIF_MASK (1 << V_GIF_SHIFT) + #define V_INTR_PRIO_SHIFT 16 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 90a9de30f8..b6ad425cca 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -110,6 +110,17 @@ static inline bool is_efer_invalid_state (CPUX86State *env) return false; } +static inline bool virtual_gif_enabled(CPUX86State *env, uint32_t *int_ctl) +{ + if (likely(env->hflags & HF_GUEST_MASK)) { + *int_ctl = x86_ldl_phys(env_cpu(env), + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); + return (env->features[FEAT_SVM] & CPUID_SVM_VGIF) + && (*int_ctl & V_GIF_ENABLED_MASK); + } + return false; +} + void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { CPUState *cs = env_cpu(env); @@ -503,13 +514,29 @@ void helper_vmsave(CPUX86State *env, int aflag) void helper_stgi(CPUX86State *env) { cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0, GETPC()); - env->hflags2 |= HF2_GIF_MASK; + + CPUState *cs = env_cpu(env); + uint32_t int_ctl; + if (virtual_gif_enabled(env, &int_ctl)) { + x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), + int_ctl | V_GIF_MASK); + } else { + env->hflags2 |= HF2_GIF_MASK; + } } void helper_clgi(CPUX86State *env) { cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0, GETPC()); - env->hflags2 &= ~HF2_GIF_MASK; + + CPUState *cs = env_cpu(env); + uint32_t int_ctl; + if (virtual_gif_enabled(env, &int_ctl)) { + x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), + int_ctl & ~V_GIF_MASK); + } else { + env->hflags2 &= ~HF2_GIF_MASK; + } } bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
v2->v3: moved guest check into virtual_gif_enabled VGIF allows STGI and CLGI to execute in guest mode and control virtual interrupts in guest mode. When the VGIF feature is enabled then: * executing STGI in the guest sets bit 9 of the VMCB offset 60h. * executing CLGI in the guest clears bit 9 of the VMCB offset 60h. Signed-off-by: Lara Lazier <laramglazier@gmail.com> --- target/i386/cpu.c | 3 ++- target/i386/svm.h | 6 ++++++ target/i386/tcg/sysemu/svm_helper.c | 31 +++++++++++++++++++++++++++-- 3 files changed, 37 insertions(+), 3 deletions(-)