diff mbox series

[v3,36/37] target/riscv: RV64 Only 32-bit Packing Instructions

Message ID 20210624105521.3964-37-zhiwei_liu@c-sky.com
State New
Headers show
Series target/riscv: support packed extension v0.9.4 | expand

Commit Message

LIU Zhiwei June 24, 2021, 10:55 a.m. UTC 
Concat two 32-bit elements to form a 64-bit element.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/helper.h                   |  5 +++
 target/riscv/insn32.decode              |  5 +++
 target/riscv/insn_trans/trans_rvp.c.inc |  6 ++++
 target/riscv/packed_helper.c            | 41 +++++++++++++++++++++++++
 4 files changed, 57 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b998c86abf..bfcf0ff761 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1474,3 +1474,8 @@  DEF_HELPER_3(smdrs32, i64, env, i64, i64)
 DEF_HELPER_3(smxds32, i64, env, i64, i64)
 
 DEF_HELPER_3(sraiw_u, i64, env, i64, i64)
+
+DEF_HELPER_3(pkbb32, i64, env, i64, i64)
+DEF_HELPER_3(pkbt32, i64, env, i64, i64)
+DEF_HELPER_3(pktt32, i64, env, i64, i64)
+DEF_HELPER_3(pktb32, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8e8aca4ea1..65682f70b5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1097,3 +1097,8 @@  smdrs32    0110100  ..... ..... 010 ..... 1110111 @r
 smxds32    0111100  ..... ..... 010 ..... 1110111 @r
 
 sraiw_u    0011010  ..... ..... 001 ..... 1110111 @sh5
+
+pkbb32     0000111  ..... ..... 010 ..... 1110111 @r
+pkbt32     0001111  ..... ..... 010 ..... 1110111 @r
+pktt32     0010111  ..... ..... 010 ..... 1110111 @r
+pktb32     0011111  ..... ..... 010 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 68c1ef9f48..7505a0f89b 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1147,3 +1147,9 @@  GEN_RVP64_R_OOL(smxds32);
 
 /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
 GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u);
+
+/* (RV64 Only) 32-bit Packing Instructions */
+GEN_RVP64_R_OOL(pkbb32);
+GEN_RVP64_R_OOL(pkbt32);
+GEN_RVP64_R_OOL(pktt32);
+GEN_RVP64_R_OOL(pktb32);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 42f1d96fa5..3f4bc593f9 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3808,3 +3808,44 @@  static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR64_64_64(sraiw_u, 1, 8);
+
+/* (RV64 Only)  32-bit packing instructions here */
+static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i)];
+    d[H4(i + 1)] = a[H4(i)];
+}
+
+RVPR64_64_64(pkbb32, 2, 4);
+
+static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i + 1)];
+    d[H4(i + 1)] = a[H4(i)];
+}
+
+RVPR64_64_64(pkbt32, 2, 4);
+
+static inline void do_pktb32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i)];
+    d[H4(i + 1)] = a[H4(i + 1)];
+}
+
+RVPR64_64_64(pktb32, 2, 4);
+
+static inline void do_pktt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i + 1)];
+    d[H4(i + 1)] = a[H4(i + 1)];
+}
+
+RVPR64_64_64(pktt32, 2, 4);