Message ID | 20210617093134.900014-38-pbonzini@redhat.com |
---|---|
State | New |
Headers | show
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Thu, 17 Jun 2021 02:32:02 -0700 (PDT) From: Paolo Bonzini <pbonzini@redhat.com> To: qemu-devel@nongnu.org Subject: [PULL 37/45] target/i386: Added Intercept CR0 writes check Date: Thu, 17 Jun 2021 11:31:26 +0200 Message-Id: <20210617093134.900014-38-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617093134.900014-1-pbonzini@redhat.com> References: <20210617093134.900014-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Lara Lazier <laramglazier@gmail.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
[PULL,01/45] vnc: avoid deprecation warnings for SASL on OS X
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diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 0cef2f1a4c..db0d8a9d79 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { switch (reg) { case 0: + /* + * If we reach this point, the CR0 write intercept is disabled. + * But we could still exit if the hypervisor has requested the selective + * intercept for bits other than TS and MP + */ + if (cpu_svm_has_intercept(env, SVM_EXIT_CR0_SEL_WRITE) && + ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) { + cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC()); + } cpu_x86_update_cr0(env, t0); break; case 3: