[PULL,v3,14/42] MAINTAINERS: Update the RISC-V CPU Maintainers

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers
Date: Tue, 11 May 2021 20:19:23 +1000
Message-Id: <20210511101951.165287-15-alistair.francis@wdc.com>
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Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
 Bin Meng <bin.meng@windriver.com>,
 =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>,
 qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>,
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Message ID	20210511101951.165287-15-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: HF9grLUzryuz3n5lz8Zuor6rjL6Wei0ZJk0ppm+0DtzFXLZxW8UPI/sFtB0Z/dSkLAi7i0yYHd RdCClAul+0MMbr+M1wb5NoOSJD25MFiDCdVVVcUXLJ7jmwjR5tMGaAoT/aWu8VNLlCA3SyV6C/ AubSmAMeLSOZqDBzaBxnI+KL36bupmgCOInORcIm3KT9KSNHU+f3ompfEBM46+zJ6Q9IsljWWx J4Szmofg0bJ3NUC0TZs7g1keqDmcoE5WPzfYSZ3+4FoAtHxtk6RMfM/YM95rD0idmXOJRjbuMm HIA= IronPort-SDR: XAnVxEF5C3+pUudpYDgPj7q/enVmp6bc71mc0VX2vomzZ40vpzAZZpPXHdWIzkleTg55v7F50s Zo76C3lG/Y3/BvuRiNYFG0EyUKc2Ilobw6EA6qk3wUv8DIUeEBlezzInX5kwx1G6tgwe+QktMS OZa/WOLcwtrTfbDHxDSlpVErjggNF7Lf5zVVBrdry8bP98fkqPv3Jj1IO8zTKbCc1+wdR2iRjp zsFp5wnHe3NfT5P4N1Ik0JMUdbtT4IYJo8oS/fpWaSDT8ij1SiOthYSphvZOB9tpAYR/e+PsnV ZQIlq4gVo7pwjdATxuF5TMTV IronPort-SDR: g46sVhfQqGDgqq+vPEBe2vTi9r3tKoAxNh6VODK9qsIiFX/9rhiMFucJSx1uvQEWomdeOuBB3z 01t0vSgyDOmJeI1+Vyj+IyOJ5m5Bsa7Y8Pck1lKjDADdpVE4vJM/s2kauKK3fCRLWDYv13pZF7 cnxg5+nosmytC5Haybrsfsfyp9JfmBgSR0QhniV9R9B6a0j9MhsE9qNkW+xyrLDwRoEs5xvLAO 6KV1Kdwg3keYWliBxIbkeo/13MgijzXfG+9avKUcYktJRqpKw72D2QahNu3XbgIDgF36a0Pid6 +Bg= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: peter.maydell@linaro.org Subject: [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Date: Tue, 11 May 2021 20:19:23 +1000 Message-Id: <20210511101951.165287-15-alistair.francis@wdc.com> In-Reply-To: <20210511101951.165287-1-alistair.francis@wdc.com> References: <20210511101951.165287-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7584e029c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Bin Meng <bin.meng@windriver.com>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code \| expand [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code [PULL,v3,02/42] docs/system/generic-loader.rst: Fix style [PULL,v3,03/42] target/riscv: Align the data type of reset vector address [PULL,v3,04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] [PULL,v3,05/42] target/riscv: Add Shakti C class CPU [PULL,v3,06/42] riscv: Add initial support for Shakti C machine [PULL,v3,07/42] hw/char: Add Shakti UART emulation [PULL,v3,08/42] hw/riscv: Connect Shakti UART to Shakti platform [PULL,v3,09/42] target/riscv: Convert the RISC-V exceptions to an enum [PULL,v3,10/42] target/riscv: Use the RISCVException enum for CSR predicates [PULL,v3,11/42] target/riscv: Fix 32-bit HS mode access permissions [PULL,v3,12/42] target/riscv: Use the RISCVException enum for CSR operations [PULL,v3,13/42] target/riscv: Use RISCVException enum for CSR access [PULL,v3,14/42] MAINTAINERS: Update the RISC-V CPU Maintainers [PULL,v3,15/42] hw/opentitan: Update the interrupt layout [PULL,v3,16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine [PULL,v3,17/42] riscv: don't look at SUM when accessing memory from a debugger context [PULL,v3,18/42] target/riscv: Fixup saturate subtract function [PULL,v3,19/42] docs: Add documentation for shakti_c machine [PULL,v3,20/42] target/riscv: Fix the PMP is locked check when using TOR [PULL,v3,21/42] target/riscv: Define ePMP mseccfg [PULL,v3,22/42] target/riscv: Add the ePMP feature [PULL,v3,23/42] target/riscv: Add ePMP CSR access functions [PULL,v3,24/42] target/riscv: Implementation of enhanced PMP (ePMP) [PULL,v3,25/42] target/riscv: Add a config option for ePMP [PULL,v3,26/42] target/riscv/pmp: Remove outdated comment [PULL,v3,27/42] target/riscv: Add ePMP support for the Ibex CPU [PULL,v3,28/42] target/riscv: fix vrgather macro index variable type bug [PULL,v3,29/42] target/riscv: fix exception index on instruction access fault [PULL,v3,30/42] hw/riscv: Fix OT IBEX reset vector [PULL,v3,31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions [PULL,v3,32/42] target/riscv: fix a typo with interrupt names [PULL,v3,33/42] target/riscv: Remove the hardcoded RVXLEN macro [PULL,v3,34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro [PULL,v3,35/42] target/riscv: Remove the hardcoded HGATP_MODE macro [PULL,v3,36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro [PULL,v3,37/42] target/riscv: Remove the hardcoded SATP_MODE macro [PULL,v3,38/42] target/riscv: Remove the unused HSTATUS_WPRI macro [PULL,v3,39/42] target/riscv: Remove an unused CASE_OP_32_64 macro [PULL,v3,40/42] target/riscv: Consolidate RV32/64 32-bit instructions [PULL,v3,41/42] target/riscv: Consolidate RV32/64 16-bit instructions [PULL,v3,42/42] target/riscv: Fix the RV64H decode comment

[PULL,v3,14/42] MAINTAINERS: Update the RISC-V CPU Maintainers

Commit Message

Patch