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05 May 2021 16:03:49 -0700 IronPort-SDR: bJ2uFQdTLf6TEk5lNM9Wn+vJQYuedt0zJhm28lvCjGz0+JUozJ87tyVdOxVUTBXCUm2qiOSErh PRR9m34NymwP1FxwtZKVMfIpn7Dy6KlPAAJAtMV7rAjP5d9vA98vOMyw1LD91g55EShgFGc5Xt UEgOcfpNaEr+gA/vVf+4I3RjF6ebEGnEYbvWRiOkNQMIlbhnicGrWTdt8xUKE2iKJcu0rrqSs3 eR0q46aHOo/6N33gqTqaQeJxE8jsgtuYmA5Xbo6thxu/KJqxb7X115zATRnflqlEsEeTZ5xfnr mxU= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.46]) by uls-op-cesaip01.wdc.com with ESMTP; 05 May 2021 16:25:06 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Date: Thu, 6 May 2021 09:23:03 +1000 Message-Id: <20210505232312.4175486-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index add734bbbd..7e879fb9ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,12 +54,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 04ac03f8c9..3191fd0082 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); }