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[PULL,03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes

Message ID 20210502161538.534038-4-f4bug@amsat.org
State New
Headers show
Series [PULL,01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ | expand

Commit Message

Philippe Mathieu-Daudé May 2, 2021, 4:15 p.m. UTC 
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":

The Read/Write Previous GPR opcodes "require CP0 privilege".

Add the missing CP0 checks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
---
 target/mips/translate.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5dad75cdf37..8a0a2197426 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18969,9 +18969,11 @@  static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
             }
             break;
         case NM_RDPGPR:
+            check_cp0_enabled(ctx);
             gen_load_srsgpr(rs, rt);
             break;
         case NM_WRPGPR:
+            check_cp0_enabled(ctx);
             gen_store_srsgpr(rs, rt);
             break;
         case NM_WAIT: