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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:10 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings Date: Fri, 30 Apr 2021 15:12:57 +0800 Message-Id: <20210430071302.1489082-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use "static const char * const" for clint_compat hw/riscv/sifive_u.c | 6 +++++- hw/riscv/spike.c | 6 +++++- hw/riscv/virt.c | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1b8af0c07a..fd5cf7513b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -99,6 +99,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; static const char * const ethclk_names[2] = { "pclk", "hclk" }; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; if (ms->dtb) { fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); @@ -210,7 +213,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, nodename = g_strdup_printf("/soc/clint@%lx", (long)memmap[SIFIVE_U_DEV_CLINT].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, nodename, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 0x0, memmap[SIFIVE_U_DEV_CLINT].size); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ec7cb2f707..f094bb2158 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -60,6 +60,9 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; char *core_name, *cpu_name, *intc_name; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -153,7 +156,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, (memmap[SPIKE_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 992f1c58a9..4b32dc734f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -195,6 +195,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, char *name, *clint_name, *plic_name, *clust_name; hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; if (mc->dtb) { fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); @@ -300,7 +303,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",