| Message ID | 20210427171649.364699-16-luis.pires@eldorado.org.br |
|---|---|
| State | New |
| Headers | show |
| Series | Base for adding PowerPC 64-bit instructions | expand |
On 4/27/21 10:16 AM, Luis Pires wrote: > Prefixed instructions were introduced in Power ISA 3.1 > > Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> > --- > target/ppc/translate.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 7422ea4e13..f4802a4f08 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7837,7 +7837,11 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, > > static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) > { > - /* TODO: Check ctx->insns_flags* for whether prefixes are supported. */ > + if (!(ctx->insns_flags2 & PPC2_ISA310)) { > + /* Prefixed instructions are not supported */ > + return false; > + } Patch 11 introduced REQUIRE_INSNS_FLAGS; this pattern calls for the introduction of REQUIRE_INSNS_FLAGS2, as you'll need it later. Fold this back into patch 8, or move this to be patch 9, so that we don't have a range of patches which accept invalid instructions. r~
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7422ea4e13..f4802a4f08 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7837,7 +7837,11 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) { - /* TODO: Check ctx->insns_flags* for whether prefixes are supported. */ + if (!(ctx->insns_flags2 & PPC2_ISA310)) { + /* Prefixed instructions are not supported */ + return false; + } + return opc1(insn) == 1; }
Prefixed instructions were introduced in Power ISA 3.1 Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> --- target/ppc/translate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)