@@ -38,9 +38,6 @@ typedef struct ARMCPUInfo {
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
-void arm_cpu_register(const ARMCPUInfo *info);
-void aarch64_cpu_register(const ARMCPUInfo *info);
-
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
new file mode 100644
@@ -0,0 +1,28 @@
+/*
+ * QEMU ARM CPU models (32bit)
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef ARM_CPU32_H
+#define ARM_CPU32_H
+
+void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
+void arm32_cpu_class_init(ObjectClass *oc, void *data);
+void arm32_cpu_register(const ARMCPUInfo *info);
+
+#endif /* ARM_CPU32_H */
@@ -30,6 +30,7 @@
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#endif /* CONFIG_TCG */
+#include "cpu32.h"
#include "internals.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
@@ -854,7 +855,7 @@ static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#endif
-static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -1855,17 +1856,6 @@ static Property arm_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
-static gchar *arm_gdb_arch_name(CPUState *cs)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- return g_strdup("iwmmxt");
- }
- return g_strdup("arm");
-}
-
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -1898,10 +1888,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
- cc->gdb_read_register = arm_cpu_gdb_read_register;
- cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
@@ -1910,9 +1897,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
#endif
- cc->gdb_num_core_regs = 26;
- cc->gdb_core_xml_file = "arm-core.xml";
- cc->gdb_arch_name = arm_gdb_arch_name;
+
cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
@@ -1920,6 +1905,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops = &arm_tcg_ops;
#endif /* CONFIG_TCG */
+
+ arm32_cpu_class_init(oc, data);
}
#ifdef CONFIG_KVM
@@ -1942,38 +1929,6 @@ static const TypeInfo host_arm_cpu_type_info = {
#endif
-static void arm_cpu_instance_init(Object *obj)
-{
- ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
-
- acc->info->initfn(obj);
- arm_cpu_post_init(obj);
-}
-
-static void cpu_register_class_init(ObjectClass *oc, void *data)
-{
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
-
- acc->info = data;
-}
-
-void arm_cpu_register(const ARMCPUInfo *info)
-{
- TypeInfo type_info = {
- .parent = TYPE_ARM_CPU,
- .instance_size = sizeof(ARMCPU),
- .instance_align = __alignof__(ARMCPU),
- .instance_init = arm_cpu_instance_init,
- .class_size = sizeof(ARMCPUClass),
- .class_init = info->class_init ?: cpu_register_class_init,
- .class_data = (void *)info,
- };
-
- type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
- type_register(&type_info);
- g_free((void *)type_info.name);
-}
-
static const TypeInfo arm_cpu_type_info = {
.name = TYPE_ARM_CPU,
.parent = TYPE_CPU,
new file mode 100644
@@ -0,0 +1,118 @@
+/*
+ * QEMU ARM CPU models (32bit)
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/qemu-print.h"
+#include "qemu-common.h"
+#include "target/arm/idau.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "cpu.h"
+#include "cpregs.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+#include "hw/qdev-properties.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/loader.h"
+#include "hw/boards.h"
+#endif
+#include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
+#include "sysemu/hw_accel.h"
+#include "kvm_arm.h"
+#include "disas/capstone.h"
+#include "fpu/softfloat.h"
+#include "cpu-mmu.h"
+#include "cpu32.h"
+
+/* we can move this to tcg/ after the cleanup of ARM boards configurations */
+static const ARMCPUInfo arm32_cpus[] = {
+};
+
+static gchar *arm_gdb_arch_name(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ return g_strdup("iwmmxt");
+ }
+ return g_strdup("arm");
+}
+
+void arm32_cpu_class_init(ObjectClass *oc, void *data)
+{
+ CPUClass *cc = CPU_CLASS(oc);
+
+ cc->gdb_read_register = arm_cpu_gdb_read_register;
+ cc->gdb_write_register = arm_cpu_gdb_write_register;
+ cc->gdb_num_core_regs = 26;
+ cc->gdb_core_xml_file = "arm-core.xml";
+ cc->gdb_arch_name = arm_gdb_arch_name;
+ cc->dump_state = arm_cpu_dump_state;
+}
+
+static void arm32_cpu_instance_init(Object *obj)
+{
+ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
+
+ acc->info->initfn(obj);
+ arm_cpu_post_init(obj);
+}
+
+static void arm32_cpu_register_class_init(ObjectClass *oc, void *data)
+{
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+
+ acc->info = data;
+}
+
+void arm32_cpu_register(const ARMCPUInfo *info)
+{
+ TypeInfo type_info = {
+ .parent = TYPE_ARM_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .instance_align = __alignof__(ARMCPU),
+ .instance_init = arm32_cpu_instance_init,
+ .class_size = sizeof(ARMCPUClass),
+ .class_init = info->class_init ?: arm32_cpu_register_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
+ type_register(&type_info);
+ g_free((void *)type_info.name);
+}
+
+static void arm32_cpu_register_types(void)
+{
+ const size_t cpu_count = ARRAY_SIZE(arm32_cpus);
+
+ if (cpu_count) {
+ size_t i;
+
+ for (i = 0; i < cpu_count; ++i) {
+ arm32_cpu_register(&arm32_cpus[i]);
+ }
+ }
+}
+
+type_init(arm32_cpu_register_types)
@@ -846,7 +846,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
}
-void aarch64_cpu_register(const ARMCPUInfo *info)
+static void aarch64_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,
@@ -19,6 +19,7 @@
#include "hw/boards.h"
#endif
#include "cpregs.h"
+#include "cpu32.h"
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -1071,7 +1072,7 @@ static void arm_tcg_cpu_register_types(void)
type_register_static(&idau_interface_type_info);
for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
- arm_cpu_register(&arm_tcg_cpus[i]);
+ arm32_cpu_register(&arm_tcg_cpus[i]);
}
}
@@ -2,12 +2,12 @@ arm_ss = ss.source_set()
arm_ss.add(files(
'cpregs.c',
'cpu.c',
+ 'cpu32.c',
'cpu-common.c',
'cpu-mmu.c',
'cpu-vfp.c',
'cpustate-list.c',
'gdbstub.c',
- 'cpu_tcg.c',
))
arm_ss.add(zlib)
@@ -18,6 +18,10 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'gdbstub64.c',
))
+arm_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'cpu_tcg.c',
+))
+
arm_softmmu_ss = ss.source_set()
arm_softmmu_ss.add(files(
'arch_dump.c',
In the ARM CPU class hierarchy, the ancestor TYPE_ARM_CPU is fundamentally a 32 bit CPU Class. The child TYPE_AARCH64_CPU overrides the class to make it a 64 bit CPU Class. Explicitly put the 32bit CPU Class implementation in a cpu32.c, along with the 32bit CPU Class model registration function. In later changes, we will further split 32bit and 64bit code. Signed-off-by: Claudio Fontana <cfontana@suse.de> --- target/arm/cpu-qom.h | 3 -- target/arm/cpu32.h | 28 ++++++++++ target/arm/cpu.c | 55 ++----------------- target/arm/cpu32.c | 118 +++++++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 3 +- target/arm/meson.build | 6 ++- 7 files changed, 159 insertions(+), 56 deletions(-) create mode 100644 target/arm/cpu32.h create mode 100644 target/arm/cpu32.c