diff mbox series

[2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines

Message ID 20210331021825.537484-2-bmeng.cn@gmail.com
State New
Headers show
Series [1/2] target/riscv: csr: Fix hmode32() for RV64 | expand

Commit Message

Bin Meng March 31, 2021, 2:18 a.m. UTC 
The following check:

    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
        return -RISCV_EXCP_ILLEGAL_INST;
    }

is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 target/riscv/csr.c | 24 ------------------------
 1 file changed, 24 deletions(-)

Comments

Alistair Francis March 31, 2021, 3:51 p.m. UTC | #1 
On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The following check:
>
>     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>         return -RISCV_EXCP_ILLEGAL_INST;
>     }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  target/riscv/csr.c | 24 ------------------------
>  1 file changed, 24 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 2bad396f64..7c24318f75 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -193,11 +193,6 @@ static int pmp(CPURISCVState *env, int csrno)
>  /* User Floating-Point CSRs */
>  static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -#if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
> -#endif
>      *val = riscv_cpu_get_fflags(env);
>      return 0;
>  }
> @@ -205,9 +200,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
>      env->mstatus |= MSTATUS_FS;
>  #endif
>      riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> @@ -216,11 +208,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>
>  static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -#if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
> -#endif
>      *val = env->frm;
>      return 0;
>  }
> @@ -228,9 +215,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
>      env->mstatus |= MSTATUS_FS;
>  #endif
>      env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> @@ -239,11 +223,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>
>  static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -#if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
> -#endif
>      *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>          | (env->frm << FSR_RD_SHIFT);
>      if (vs(env, csrno) >= 0) {
> @@ -256,9 +235,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> -        return -RISCV_EXCP_ILLEGAL_INST;
> -    }
>      env->mstatus |= MSTATUS_FS;
>  #endif
>      env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> --
> 2.25.1
>
>
Bin Meng June 15, 2021, 9:07 a.m. UTC | #2 
Hi Alistair,

On Wed, Mar 31, 2021 at 11:53 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > The following check:
> >
> >     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> >         return -RISCV_EXCP_ILLEGAL_INST;
> >     }
> >
> > is redundant in fflags/frm/fcsr read/write routines, as the check was
> > already done in fs().
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>

It looks like this patch was not applied anywhere?

Regards,
Bin
Alistair Francis June 15, 2021, 10:42 a.m. UTC | #3 
On Tue, Jun 15, 2021 at 7:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Alistair,
>
> On Wed, Mar 31, 2021 at 11:53 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > The following check:
> > >
> > >     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> > >         return -RISCV_EXCP_ILLEGAL_INST;
> > >     }
> > >
> > > is redundant in fflags/frm/fcsr read/write routines, as the check was
> > > already done in fs().
> > >
> > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> >
>
> It looks like this patch was not applied anywhere?

Nope, it doesn't appear to have been. Do you mind re-sending it?

Alistair

>
> Regards,
> Bin
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2bad396f64..7c24318f75 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -193,11 +193,6 @@  static int pmp(CPURISCVState *env, int csrno)
 /* User Floating-Point CSRs */
 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = riscv_cpu_get_fflags(env);
     return 0;
 }
@@ -205,9 +200,6 @@  static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -216,11 +208,6 @@  static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 
 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = env->frm;
     return 0;
 }
@@ -228,9 +215,6 @@  static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -239,11 +223,6 @@  static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 
 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
         | (env->frm << FSR_RD_SHIFT);
     if (vs(env, csrno) >= 0) {
@@ -256,9 +235,6 @@  static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;