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[1/2] target/riscv: csr: Fix hmode32() for RV64

Message ID 20210331021825.537484-1-bmeng.cn@gmail.com
State New
Headers show
Series [1/2] target/riscv: csr: Fix hmode32() for RV64 | expand

Commit Message

Bin Meng March 31, 2021, 2:18 a.m. UTC
hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alistair Francis March 31, 2021, 3:03 p.m. UTC | #1
On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Thanks for the patch.

There is already a patch on list to fix this: "target/riscv: Fix
32-bit HS mode access permissions"

Alistair

> ---
>
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..2bad396f64 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno)
>  static int hmode32(CPURISCVState *env, int csrno)
>  {
>      if (!riscv_cpu_is_32bit(env)) {
> -        return 0;
> +        return -RISCV_EXCP_ILLEGAL_INST;
>      }
>
>      return hmode(env, csrno);
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..2bad396f64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -177,7 +177,7 @@  static int hmode(CPURISCVState *env, int csrno)
 static int hmode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_cpu_is_32bit(env)) {
-        return 0;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     return hmode(env, csrno);