@@ -9,6 +9,7 @@
#define NVME_DEFAULT_ZONE_SIZE (128 * MiB)
#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
+#define NVME_MAX_COMMANDS 0x100
/*
* Subsystem namespace list for allocated namespaces should be larger than
@@ -28,6 +29,7 @@ typedef struct NvmeParams {
bool use_intel_id;
uint8_t zasl;
bool legacy_cmb;
+ uint16_t oncs;
} NvmeParams;
typedef struct NvmeAsyncEvent {
@@ -210,6 +212,11 @@ typedef struct NvmeCtrl {
NvmeCQueue admin_cq;
NvmeIdCtrl id_ctrl;
NvmeFeatureVal features;
+
+ struct {
+ uint32_t nvm[NVME_MAX_COMMANDS];
+ uint32_t zoned[NVME_MAX_COMMANDS];
+ } iocs;
} NvmeCtrl;
static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
@@ -84,6 +84,11 @@
* the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
* defaulting to the value of `mdts`).
*
+ * - `oncs`
+ * This field indicates the optional NVM commands and features supported
+ * by the controller. To add support for the optional feature, needs to
+ * set the corresponding support indicated bit.
+ *
* nvme namespace device parameters
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* - `subsys`
@@ -185,7 +190,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
[NVME_TIMESTAMP] = NVME_FEAT_CAP_CHANGE,
};
-static const uint32_t nvme_cse_acs[256] = {
+static const uint32_t nvme_cse_acs[NVME_MAX_COMMANDS] = {
[NVME_ADM_CMD_DELETE_SQ] = NVME_CMD_EFF_CSUPP,
[NVME_ADM_CMD_CREATE_SQ] = NVME_CMD_EFF_CSUPP,
[NVME_ADM_CMD_GET_LOG_PAGE] = NVME_CMD_EFF_CSUPP,
@@ -199,30 +204,7 @@ static const uint32_t nvme_cse_acs[256] = {
[NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC,
};
-static const uint32_t nvme_cse_iocs_none[256];
-
-static const uint32_t nvme_cse_iocs_nvm[256] = {
- [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP,
- [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP,
-};
-
-static const uint32_t nvme_cse_iocs_zoned[256] = {
- [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP,
- [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP,
- [NVME_CMD_ZONE_APPEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_ZONE_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
- [NVME_CMD_ZONE_MGMT_RECV] = NVME_CMD_EFF_CSUPP,
-};
+static const uint32_t nvme_cse_iocs_none[NVME_MAX_COMMANDS];
static void nvme_process_sq(void *opaque);
@@ -3071,17 +3053,17 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
switch (NVME_CC_CSS(n->bar.cc)) {
case NVME_CC_CSS_NVM:
- src_iocs = nvme_cse_iocs_nvm;
+ src_iocs = n->iocs.nvm;
/* fall through */
case NVME_CC_CSS_ADMIN_ONLY:
break;
case NVME_CC_CSS_CSI:
switch (csi) {
case NVME_CSI_NVM:
- src_iocs = nvme_cse_iocs_nvm;
+ src_iocs = n->iocs.nvm;
break;
case NVME_CSI_ZONED:
- src_iocs = nvme_cse_iocs_zoned;
+ src_iocs = n->iocs.zoned;
break;
}
}
@@ -3684,6 +3666,10 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR;
}
+ if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES) && sel) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
/*
@@ -3766,6 +3752,9 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
result = n->features.async_config;
goto out;
case NVME_TIMESTAMP:
+ if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
return nvme_get_feature_timestamp(n, req);
default:
break;
@@ -3843,6 +3832,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
trace_pci_nvme_setfeat(nvme_cid(req), nsid, fid, save, dw11);
+ if (save && !(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
if (save && !(nvme_feature_cap[fid] & NVME_FEAT_CAP_SAVE)) {
return NVME_FID_NOT_SAVEABLE | NVME_DNR;
}
@@ -3959,6 +3952,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
n->features.async_config = dw11;
break;
case NVME_TIMESTAMP:
+ if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
return nvme_set_feature_timestamp(n, req);
case NVME_COMMAND_SET_PROFILE:
if (dw11 & 0x1ff) {
@@ -4201,14 +4197,14 @@ static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns)
switch (ns->csi) {
case NVME_CSI_NVM:
if (NVME_CC_CSS(n->bar.cc) != NVME_CC_CSS_ADMIN_ONLY) {
- ns->iocs = nvme_cse_iocs_nvm;
+ ns->iocs = n->iocs.nvm;
}
break;
case NVME_CSI_ZONED:
if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_CSI) {
- ns->iocs = nvme_cse_iocs_zoned;
+ ns->iocs = n->iocs.zoned;
} else if (NVME_CC_CSS(n->bar.cc) == NVME_CC_CSS_NVM) {
- ns->iocs = nvme_cse_iocs_nvm;
+ ns->iocs = n->iocs.nvm;
}
break;
}
@@ -4838,6 +4834,40 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
}
}
+static void nvme_init_cse_iocs(NvmeCtrl *n)
+{
+ uint16_t oncs = n->params.oncs;
+
+ n->iocs.nvm[NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC;
+ n->iocs.nvm[NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC;
+ n->iocs.nvm[NVME_CMD_READ] = NVME_CMD_EFF_CSUPP;
+
+ if (oncs & NVME_ONCS_WRITE_ZEROES) {
+ n->iocs.nvm[NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP |
+ NVME_CMD_EFF_LBCC;
+ }
+
+ if (oncs & NVME_ONCS_COMPARE) {
+ n->iocs.nvm[NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP;
+ }
+
+ if (oncs & NVME_ONCS_DSM) {
+ n->iocs.nvm[NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC;
+ }
+
+ if (oncs & NVME_ONCS_COPY) {
+ n->iocs.nvm[NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC;
+ }
+
+ memcpy(n->iocs.zoned, n->iocs.nvm, sizeof(n->iocs.nvm));
+
+ n->iocs.zoned[NVME_CMD_ZONE_APPEND] = NVME_CMD_EFF_CSUPP |
+ NVME_CMD_EFF_LBCC;
+ n->iocs.zoned[NVME_CMD_ZONE_MGMT_SEND] = NVME_CMD_EFF_CSUPP |
+ NVME_CMD_EFF_LBCC;
+ n->iocs.zoned[NVME_CMD_ZONE_MGMT_RECV] = NVME_CMD_EFF_CSUPP;
+}
+
static void nvme_init_state(NvmeCtrl *n)
{
n->num_namespaces = NVME_MAX_NAMESPACES;
@@ -4850,6 +4880,8 @@ static void nvme_init_state(NvmeCtrl *n)
n->features.temp_thresh_hi = NVME_TEMPERATURE_WARNING;
n->starttime_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
+
+ nvme_init_cse_iocs(n);
}
static int nvme_attach_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
@@ -5091,9 +5123,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->sqes = (0x6 << 4) | 0x6;
id->cqes = (0x4 << 4) | 0x4;
id->nn = cpu_to_le32(n->num_namespaces);
- id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
- NVME_ONCS_FEATURES | NVME_ONCS_DSM |
- NVME_ONCS_COMPARE | NVME_ONCS_COPY);
+ id->oncs = cpu_to_le16(n->params.oncs);
/*
* NOTE: If this device ever supports a command set that does NOT use 0x0
@@ -5239,6 +5269,9 @@ static Property nvme_props[] = {
DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),
DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0),
+ DEFINE_PROP_UINT16("oncs", NvmeCtrl, params.oncs, NVME_ONCS_WRITE_ZEROES |
+ NVME_ONCS_TIMESTAMP | NVME_ONCS_DSM |
+ NVME_ONCS_COMPARE | NVME_ONCS_FEATURES | NVME_ONCS_COPY),
DEFINE_PROP_END_OF_LIST(),
};