diff mbox series

[PULL,40/42] esp: add trivial implementation of the ESP_RFLAGS register

Message ID 20210307120850.10418-41-mark.cave-ayland@ilande.co.uk
State New
Headers show
Series [PULL,01/42] esp: checkpatch fixes | expand

Commit Message

Mark Cave-Ayland March 7, 2021, 12:08 p.m. UTC 
The bottom 5 bits contain the number of bytes remaining in the FIFO which is
trivial to implement with Fifo8 (the remaining bits are unimplemented and left
as 0 for now).

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210304221103.6369-41-mark.cave-ayland@ilande.co.uk>
---
 hw/scsi/esp.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 34dc58da58..8a9b1500de 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -818,6 +818,10 @@  uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
             val = s->rregs[saddr];
         }
         break;
+     case ESP_RFLAGS:
+        /* Bottom 5 bits indicate number of bytes in FIFO */
+        val = fifo8_num_used(&s->fifo);
+        break;
     default:
         val = s->rregs[saddr];
         break;