diff mbox series

[PULL,30/42] esp: add 4 byte PDMA read and write transfers

Message ID	20210307120850.10418-31-mark.cave-ayland@ilande.co.uk
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:38 +0000 Message-Id: <20210307120850.10418-31-mark.cave-ayland@ilande.co.uk> In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [PULL 30/42] esp: add 4 byte PDMA read and write transfers Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/42] esp: checkpatch fixes \| expand [PULL,01/42] esp: checkpatch fixes [PULL,02/42] esp: rename existing ESP QOM type to SYSBUS_ESP [PULL,03/42] esp: QOMify the internal ESP device state [PULL,04/42] esp: add vmstate_esp version to embedded ESPState [PULL,05/42] esp: add trace event when receiving a TI command [PULL,06/42] esp: fix esp_reg_read() trace event [PULL,07/42] esp: add PDMA trace events [PULL,08/42] esp: determine transfer direction directly from SCSI phase [PULL,09/42] esp: introduce esp_get_tc() and esp_set_tc() [PULL,10/42] esp: introduce esp_get_stc() [PULL,11/42] esp: apply transfer length adjustment when STC is zero at TC load time [PULL,12/42] esp: remove dma_counter from ESPState [PULL,13/42] esp: remove dma_left from ESPState [PULL,14/42] esp: remove minlen restriction in handle_ti [PULL,15/42] esp: introduce esp_pdma_read() and esp_pdma_write() functions [PULL,16/42] esp: use pdma_origin directly in esp_pdma_read()/esp_pdma_write() [PULL,17/42] esp: move pdma_len and TC logic into esp_pdma_read()/esp_pdma_write() [PULL,18/42] esp: accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_buf [PULL,19/42] esp: remove buf parameter from do_cmd() [PULL,20/42] esp: remove the buf and buflen parameters from get_cmd() [PULL,21/42] esp: remove redundant pdma_start from ESPState [PULL,22/42] esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write() [PULL,23/42] esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA [PULL,24/42] esp: use in-built TC to determine PDMA transfer length [PULL,25/42] esp: remove CMD pdma_origin [PULL,26/42] esp: rename get_cmd_cb() to esp_select() [PULL,27/42] esp: fix PDMA target selection [PULL,28/42] esp: use FIFO for PDMA transfers between initiator and device [PULL,29/42] esp: remove pdma_origin from ESPState [PULL,30/42] esp: add 4 byte PDMA read and write transfers [PULL,31/42] esp: implement FIFO flush command [PULL,32/42] esp: latch individual bits in ESP_RINTR register [PULL,33/42] esp: defer command completion interrupt on incoming data transfers [PULL,34/42] esp: remove old deferred command completion mechanism [PULL,35/42] esp: raise interrupt after every non-DMA byte transferred to the FIFO [PULL,36/42] esp: add maxlen parameter to get_cmd() [PULL,37/42] esp: transition to message out phase after SATN and stop command [PULL,38/42] esp: convert ti_buf from array to Fifo8 [PULL,39/42] esp: convert cmdbuf from array to Fifo8 [PULL,40/42] esp: add trivial implementation of the ESP_RFLAGS register [PULL,41/42] esp: implement non-DMA transfers in PDMA mode [PULL,42/42] esp: add support for unaligned accesses

Commit Message

Mark Cave-Ayland March 7, 2021, 12:08 p.m. UTC

The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to
and from the target. Since the SCSI bus is 16-bits wide, use the memory API
to split a 4 byte access into 2 x 2 byte accesses.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210304221103.6369-31-mark.cave-ayland@ilande.co.uk>
---
 hw/scsi/esp.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 79b84e31d3..2dded90be6 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -1002,7 +1002,9 @@  static const MemoryRegionOps sysbus_esp_pdma_ops = {
     .write = sysbus_esp_pdma_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid.min_access_size = 1,
-    .valid.max_access_size = 2,
+    .valid.max_access_size = 4,
+    .impl.min_access_size = 1,
+    .impl.max_access_size = 2,
 };
 
 static const struct SCSIBusInfo esp_scsi_info = {
@@ -1049,7 +1051,7 @@  static void sysbus_esp_realize(DeviceState *dev, Error **errp)
                           sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
     sysbus_init_mmio(sbd, &sysbus->iomem);
     memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
-                          sysbus, "esp-pdma", 2);
+                          sysbus, "esp-pdma", 4);
     sysbus_init_mmio(sbd, &sysbus->pdma);
 
     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);