| Message ID | 20210302110955.1810487-3-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm: versal: Add support for the XRAMs | expand |
On Tue, Mar 2, 2021 at 6:10 AM Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Connect the support for the Versal Accelerator RAMs (XRAMs). > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > docs/system/arm/xlnx-versal-virt.rst | 1 + > include/hw/arm/xlnx-versal.h | 13 ++++++++++ > hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++ > 3 files changed, 50 insertions(+) > > diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst > index 2602d0f995..27f73500d9 100644 > --- a/docs/system/arm/xlnx-versal-virt.rst > +++ b/docs/system/arm/xlnx-versal-virt.rst > @@ -30,6 +30,7 @@ Implemented devices: > - 8 ADMA (Xilinx zDMA) channels > - 2 SD Controllers > - OCM (256KB of On Chip Memory) > +- XRAM (4MB of on chip Accelerator RAM) > - DDR memory > > QEMU does not yet model any other devices, including the PL and the AI Engine. > diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h > index 2b76885afd..22a8fa5d11 100644 > --- a/include/hw/arm/xlnx-versal.h > +++ b/include/hw/arm/xlnx-versal.h > @@ -14,6 +14,7 @@ > > #include "hw/sysbus.h" > #include "hw/arm/boot.h" > +#include "hw/or-irq.h" > #include "hw/sd/sdhci.h" > #include "hw/intc/arm_gicv3.h" > #include "hw/char/pl011.h" > @@ -22,6 +23,7 @@ > #include "hw/rtc/xlnx-zynqmp-rtc.h" > #include "qom/object.h" > #include "hw/usb/xlnx-usb-subsystem.h" > +#include "hw/misc/xlnx-versal-xramc.h" > > #define TYPE_XLNX_VERSAL "xlnx-versal" > OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) > @@ -31,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) > #define XLNX_VERSAL_NR_GEMS 2 > #define XLNX_VERSAL_NR_ADMAS 8 > #define XLNX_VERSAL_NR_SDS 2 > +#define XLNX_VERSAL_NR_XRAM 4 > #define XLNX_VERSAL_NR_IRQS 192 > > struct Versal { > @@ -62,6 +65,11 @@ struct Versal { > XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; > VersalUsb2 usb; > } iou; > + > + struct { > + qemu_or_irq irq_orgate; > + XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; > + } xram; > } lpd; > > /* The Platform Management Controller subsystem. */ > @@ -96,6 +104,7 @@ struct Versal { > #define VERSAL_GEM1_IRQ_0 58 > #define VERSAL_GEM1_WAKE_IRQ_0 59 > #define VERSAL_ADMA_IRQ_0 60 > +#define VERSAL_XRAM_IRQ_0 79 > #define VERSAL_RTC_APB_ERR_IRQ 121 > #define VERSAL_SD0_IRQ_0 126 > #define VERSAL_RTC_ALARM_IRQ 142 > @@ -128,6 +137,10 @@ struct Versal { > #define MM_OCM 0xfffc0000U > #define MM_OCM_SIZE 0x40000 > > +#define MM_XRAM 0xfe800000 > +#define MM_XRAMC 0xff8e0000 > +#define MM_XRAMC_SIZE 0x10000 > + > #define MM_USB2_CTRL_REGS 0xFF9D0000 > #define MM_USB2_CTRL_REGS_SIZE 0x10000 > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 628e77ef66..79609692e4 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -10,6 +10,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/units.h" > #include "qapi/error.h" > #include "qemu/log.h" > #include "qemu/module.h" > @@ -278,6 +279,40 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic) > sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); > } > > +static void versal_create_xrams(Versal *s, qemu_irq *pic) > +{ > + int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); > + DeviceState *orgate; > + int i; > + > + /* XRAM IRQs get ORed into a single line. */ > + object_initialize_child(OBJECT(s), "xram-irq-orgate", > + &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); > + orgate = DEVICE(&s->lpd.xram.irq_orgate); > + object_property_set_int(OBJECT(orgate), > + "num-lines", nr_xrams, &error_fatal); > + qdev_realize(orgate, NULL, &error_fatal); > + qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); > + > + for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { > + SysBusDevice *sbd; > + MemoryRegion *mr; > + > + object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], > + TYPE_XLNX_XRAM_CTRL); > + sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); > + sysbus_realize(sbd, &error_fatal); > + > + mr = sysbus_mmio_get_region(sbd, 0); > + memory_region_add_subregion(&s->mr_ps, > + MM_XRAMC + i * MM_XRAMC_SIZE, mr); > + mr = sysbus_mmio_get_region(sbd, 1); > + memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); > + > + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); > + } > +} > + > /* This takes the board allocated linear DDR memory and creates aliases > * for each split DDR range/aperture on the Versal address map. > */ > @@ -363,6 +398,7 @@ static void versal_realize(DeviceState *dev, Error **errp) > versal_create_admas(s, pic); > versal_create_sds(s, pic); > versal_create_rtc(s, pic); > + versal_create_xrams(s, pic); > versal_map_ddr(s); > versal_unimp(s); > > -- > 2.25.1 > >
On 3/2/21 12:09 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Connect the support for the Versal Accelerator RAMs (XRAMs). > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> > --- > docs/system/arm/xlnx-versal-virt.rst | 1 + > include/hw/arm/xlnx-versal.h | 13 ++++++++++ > hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++ > 3 files changed, 50 insertions(+) > > diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst > index 2602d0f995..27f73500d9 100644 > --- a/docs/system/arm/xlnx-versal-virt.rst > +++ b/docs/system/arm/xlnx-versal-virt.rst > @@ -30,6 +30,7 @@ Implemented devices: > - 8 ADMA (Xilinx zDMA) channels > - 2 SD Controllers > - OCM (256KB of On Chip Memory) > +- XRAM (4MB of on chip Accelerator RAM) > - DDR memory > > QEMU does not yet model any other devices, including the PL and the AI Engine. > diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h > index 2b76885afd..22a8fa5d11 100644 > --- a/include/hw/arm/xlnx-versal.h > +++ b/include/hw/arm/xlnx-versal.h > @@ -14,6 +14,7 @@ > > #include "hw/sysbus.h" > #include "hw/arm/boot.h" > +#include "hw/or-irq.h" > #include "hw/sd/sdhci.h" > #include "hw/intc/arm_gicv3.h" > #include "hw/char/pl011.h" > @@ -22,6 +23,7 @@ > #include "hw/rtc/xlnx-zynqmp-rtc.h" > #include "qom/object.h" > #include "hw/usb/xlnx-usb-subsystem.h" > +#include "hw/misc/xlnx-versal-xramc.h" > > #define TYPE_XLNX_VERSAL "xlnx-versal" > OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) > @@ -31,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) > #define XLNX_VERSAL_NR_GEMS 2 > #define XLNX_VERSAL_NR_ADMAS 8 > #define XLNX_VERSAL_NR_SDS 2 > +#define XLNX_VERSAL_NR_XRAM 4 > #define XLNX_VERSAL_NR_IRQS 192 > > struct Versal { > @@ -62,6 +65,11 @@ struct Versal { > XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; > VersalUsb2 usb; > } iou; > + > + struct { > + qemu_or_irq irq_orgate; > + XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; > + } xram; > } lpd; > > /* The Platform Management Controller subsystem. */ > @@ -96,6 +104,7 @@ struct Versal { > #define VERSAL_GEM1_IRQ_0 58 > #define VERSAL_GEM1_WAKE_IRQ_0 59 > #define VERSAL_ADMA_IRQ_0 60 > +#define VERSAL_XRAM_IRQ_0 79 > #define VERSAL_RTC_APB_ERR_IRQ 121 > #define VERSAL_SD0_IRQ_0 126 > #define VERSAL_RTC_ALARM_IRQ 142 > @@ -128,6 +137,10 @@ struct Versal { > #define MM_OCM 0xfffc0000U > #define MM_OCM_SIZE 0x40000 > > +#define MM_XRAM 0xfe800000 > +#define MM_XRAMC 0xff8e0000 > +#define MM_XRAMC_SIZE 0x10000 > + > #define MM_USB2_CTRL_REGS 0xFF9D0000 > #define MM_USB2_CTRL_REGS_SIZE 0x10000 > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 628e77ef66..79609692e4 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -10,6 +10,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/units.h" > #include "qapi/error.h" > #include "qemu/log.h" > #include "qemu/module.h" > @@ -278,6 +279,40 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic) > sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); > } > > +static void versal_create_xrams(Versal *s, qemu_irq *pic) > +{ > + int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); > + DeviceState *orgate; > + int i; > + > + /* XRAM IRQs get ORed into a single line. */ > + object_initialize_child(OBJECT(s), "xram-irq-orgate", > + &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); > + orgate = DEVICE(&s->lpd.xram.irq_orgate); > + object_property_set_int(OBJECT(orgate), > + "num-lines", nr_xrams, &error_fatal); > + qdev_realize(orgate, NULL, &error_fatal); > + qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); > + > + for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { > + SysBusDevice *sbd; > + MemoryRegion *mr; > + > + object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], > + TYPE_XLNX_XRAM_CTRL); > + sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); > + sysbus_realize(sbd, &error_fatal); > + > + mr = sysbus_mmio_get_region(sbd, 0); > + memory_region_add_subregion(&s->mr_ps, > + MM_XRAMC + i * MM_XRAMC_SIZE, mr); > + mr = sysbus_mmio_get_region(sbd, 1); > + memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); > + > + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); > + } > +} > + > /* This takes the board allocated linear DDR memory and creates aliases > * for each split DDR range/aperture on the Versal address map. > */ > @@ -363,6 +398,7 @@ static void versal_realize(DeviceState *dev, Error **errp) > versal_create_admas(s, pic); > versal_create_sds(s, pic); > versal_create_rtc(s, pic); > + versal_create_xrams(s, pic); > versal_map_ddr(s); > versal_unimp(s); > >
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst index 2602d0f995..27f73500d9 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -30,6 +30,7 @@ Implemented devices: - 8 ADMA (Xilinx zDMA) channels - 2 SD Controllers - OCM (256KB of On Chip Memory) +- XRAM (4MB of on chip Accelerator RAM) - DDR memory QEMU does not yet model any other devices, including the PL and the AI Engine. diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 2b76885afd..22a8fa5d11 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -14,6 +14,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/or-irq.h" #include "hw/sd/sdhci.h" #include "hw/intc/arm_gicv3.h" #include "hw/char/pl011.h" @@ -22,6 +23,7 @@ #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" #include "hw/usb/xlnx-usb-subsystem.h" +#include "hw/misc/xlnx-versal-xramc.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -31,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) #define XLNX_VERSAL_NR_GEMS 2 #define XLNX_VERSAL_NR_ADMAS 8 #define XLNX_VERSAL_NR_SDS 2 +#define XLNX_VERSAL_NR_XRAM 4 #define XLNX_VERSAL_NR_IRQS 192 struct Versal { @@ -62,6 +65,11 @@ struct Versal { XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; } iou; + + struct { + qemu_or_irq irq_orgate; + XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; + } xram; } lpd; /* The Platform Management Controller subsystem. */ @@ -96,6 +104,7 @@ struct Versal { #define VERSAL_GEM1_IRQ_0 58 #define VERSAL_GEM1_WAKE_IRQ_0 59 #define VERSAL_ADMA_IRQ_0 60 +#define VERSAL_XRAM_IRQ_0 79 #define VERSAL_RTC_APB_ERR_IRQ 121 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_RTC_ALARM_IRQ 142 @@ -128,6 +137,10 @@ struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 +#define MM_XRAM 0xfe800000 +#define MM_XRAMC 0xff8e0000 +#define MM_XRAMC_SIZE 0x10000 + #define MM_USB2_CTRL_REGS 0xFF9D0000 #define MM_USB2_CTRL_REGS_SIZE 0x10000 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 628e77ef66..79609692e4 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -10,6 +10,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" @@ -278,6 +279,40 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic) sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); } +static void versal_create_xrams(Versal *s, qemu_irq *pic) +{ + int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); + DeviceState *orgate; + int i; + + /* XRAM IRQs get ORed into a single line. */ + object_initialize_child(OBJECT(s), "xram-irq-orgate", + &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); + orgate = DEVICE(&s->lpd.xram.irq_orgate); + object_property_set_int(OBJECT(orgate), + "num-lines", nr_xrams, &error_fatal); + qdev_realize(orgate, NULL, &error_fatal); + qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); + + for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { + SysBusDevice *sbd; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], + TYPE_XLNX_XRAM_CTRL); + sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); + sysbus_realize(sbd, &error_fatal); + + mr = sysbus_mmio_get_region(sbd, 0); + memory_region_add_subregion(&s->mr_ps, + MM_XRAMC + i * MM_XRAMC_SIZE, mr); + mr = sysbus_mmio_get_region(sbd, 1); + memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); + + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); + } +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -363,6 +398,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_admas(s, pic); versal_create_sds(s, pic); versal_create_rtc(s, pic); + versal_create_xrams(s, pic); versal_map_ddr(s); versal_unimp(s);