diff mbox series

[37/38] target/riscv: RV64 Only 32-bit Packing Instructions

Message ID 20210212150256.885-38-zhiwei_liu@c-sky.com
State New
Headers show
Series target/riscv: support packed extension v0.9.2 | expand

Commit Message

LIU Zhiwei Feb. 12, 2021, 3:02 p.m. UTC 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/helper.h                   |  5 +++
 target/riscv/insn32-64.decode           |  5 +++
 target/riscv/insn_trans/trans_rvp.c.inc |  6 ++++
 target/riscv/packed_helper.c            | 41 +++++++++++++++++++++++++
 4 files changed, 57 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d3dd1fb248..6e9c205481 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1471,4 +1471,9 @@  DEF_HELPER_3(smdrs32, tl, env, tl, tl)
 DEF_HELPER_3(smxds32, tl, env, tl, tl)
 
 DEF_HELPER_3(sraiw_u, tl, env, tl, tl)
+
+DEF_HELPER_3(pkbb32, tl, env, tl, tl)
+DEF_HELPER_3(pkbt32, tl, env, tl, tl)
+DEF_HELPER_3(pktt32, tl, env, tl, tl)
+DEF_HELPER_3(pktb32, tl, env, tl, tl)
 #endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 32066d3ac2..62cfd74830 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -166,3 +166,8 @@  smdrs32    0110100  ..... ..... 010 ..... 1111111 @r
 smxds32    0111100  ..... ..... 010 ..... 1111111 @r
 
 sraiw_u    0011010  ..... ..... 001 ..... 1111111 @sh5
+
+pkbb32     0000111  ..... ..... 010 ..... 1111111 @r
+pkbt32     0001111  ..... ..... 010 ..... 1111111 @r
+pktt32     0010111  ..... ..... 010 ..... 1111111 @r
+pktb32     0011111  ..... ..... 010 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 57827d2e15..868b308ed6 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1215,4 +1215,10 @@  GEN_RVP_R_OOL(smxds32);
 
 /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
 GEN_RVP_SHIFTI(sraiw_u, sraiw_u, NULL);
+
+/* (RV64 Only) 32-bit Packing Instructions */
+GEN_RVP_R_OOL(pkbb32);
+GEN_RVP_R_OOL(pkbt32);
+GEN_RVP_R_OOL(pktt32);
+GEN_RVP_R_OOL(pktb32);
 #endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 69a7788e99..e9add8fe5b 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3818,4 +3818,45 @@  static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR(sraiw_u, 1, sizeof(target_ulong));
+
+/* (RV64 Only)  32-bit packing instructions here */
+static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i)];
+    d[H4(i + 1)] = a[H4(i)];
+}
+
+RVPR(pkbb32, 2, 4);
+
+static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i + 1)];
+    d[H4(i + 1)] = a[H4(i)];
+}
+
+RVPR(pkbt32, 2, 4);
+
+static inline void do_pktb32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i)];
+    d[H4(i + 1)] = a[H4(i + 1)];
+}
+
+RVPR(pktb32, 2, 4);
+
+static inline void do_pktt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+    d[H4(i)] = b[H4(i + 1)];
+    d[H4(i + 1)] = a[H4(i + 1)];
+}
+
+RVPR(pktt32, 2, 4);
 #endif