| Message ID | 20210209193018.31339-31-mark.cave-ayland@ilande.co.uk |
|---|---|
| State | New |
| Headers | show |
| Series | esp: consolidate PDMA transfer buffers and other fixes | expand |
On 2/9/21 8:30 PM, Mark Cave-Ayland wrote: > The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to > and from the target. Since the SCSI bus is 16-bits wide, use the memory API > to split a 4 byte access into 2 x 2 byte accesses. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > hw/scsi/esp.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Out of curiosity, what is the bus used?
On 12/02/2021 18:56, Philippe Mathieu-Daudé wrote: > On 2/9/21 8:30 PM, Mark Cave-Ayland wrote: >> The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to >> and from the target. Since the SCSI bus is 16-bits wide, use the memory API >> to split a 4 byte access into 2 x 2 byte accesses. >> >> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> >> --- >> hw/scsi/esp.c | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > Out of curiosity, what is the bus used? AFAICT it's a custom logic chip that sits on the CPU address/data buses that does the decoding between the CPU and ESP chip. Other than a simple block diagram of the Quadra there isn't much official documentation out there :/ Are you planning to review any more of this series? I'm keen to put out a (hopefully final) v3 soon, but I'll hold off for little while if you want more time to look over the remaining patches. ATB, Mark.
Hi Mark, On 2/15/21 11:35 PM, Mark Cave-Ayland wrote: > On 12/02/2021 18:56, Philippe Mathieu-Daudé wrote: > >> On 2/9/21 8:30 PM, Mark Cave-Ayland wrote: >>> The MacOS toolbox ROM performs 4 byte reads/writes when transferring >>> data to >>> and from the target. Since the SCSI bus is 16-bits wide, use the >>> memory API >>> to split a 4 byte access into 2 x 2 byte accesses. >>> >>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> >>> --- >>> hw/scsi/esp.c | 6 ++++-- >>> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> >> >> Out of curiosity, what is the bus used? > > AFAICT it's a custom logic chip that sits on the CPU address/data buses > that does the decoding between the CPU and ESP chip. Other than a simple > block diagram of the Quadra there isn't much official documentation out > there :/ OK. > Are you planning to review any more of this series? I'm keen to put out > a (hopefully final) v3 soon, but I'll hold off for little while if you > want more time to look over the remaining patches. I talked about this series with Laurent on Sunday, asking him for review help ;) I don't remember if there is any big comment to address in patches 1-14. If not I can review the missing ones there today and you could send directly a pull request for this first set, then send the rest as v3. Does that help? For the rest I doubt having time to focus before Friday. Regards, Phil.
On 16/02/2021 07:30, Philippe Mathieu-Daudé wrote: >> Are you planning to review any more of this series? I'm keen to put out >> a (hopefully final) v3 soon, but I'll hold off for little while if you >> want more time to look over the remaining patches. > > I talked about this series with Laurent on Sunday, asking him for > review help ;) I don't remember if there is any big comment to > address in patches 1-14. If not I can review the missing ones > there today and you could send directly a pull request for this > first set, then send the rest as v3. Does that help? > For the rest I doubt having time to focus before Friday. I'd prefer to merge the entire series, since there is more than one migration compatibility break for the q800 machine and I think it would be almost impossible to ensure that all test images didn't regress at some point until all patches have been applied. I should probably add that I expanded the test suite to booting 10 images from v1 to v2 across a mix of SPARC, m68k, x86_64 and hppa including both commercial and free OSs. ATB, Mark.
On 16/02/2021 07:30, Philippe Mathieu-Daudé wrote: >> Are you planning to review any more of this series? I'm keen to put out >> a (hopefully final) v3 soon, but I'll hold off for little while if you >> want more time to look over the remaining patches. > > I talked about this series with Laurent on Sunday, asking him for > review help ;) I don't remember if there is any big comment to > address in patches 1-14. If not I can review the missing ones > there today and you could send directly a pull request for this > first set, then send the rest as v3. Does that help? > For the rest I doubt having time to focus before Friday. Hi Phil/Laurent, I know you're both really busy, but gentle ping to ask if anyone is still planning to review the second half of this patchset? :) ATB, Mark.
On 2/23/21 9:24 AM, Mark Cave-Ayland wrote: > On 16/02/2021 07:30, Philippe Mathieu-Daudé wrote: > >>> Are you planning to review any more of this series? I'm keen to put out >>> a (hopefully final) v3 soon, but I'll hold off for little while if you >>> want more time to look over the remaining patches. >> >> I talked about this series with Laurent on Sunday, asking him for >> review help ;) I don't remember if there is any big comment to >> address in patches 1-14. If not I can review the missing ones >> there today and you could send directly a pull request for this >> first set, then send the rest as v3. Does that help? >> For the rest I doubt having time to focus before Friday. > > Hi Phil/Laurent, > > I know you're both really busy, but gentle ping to ask if anyone is > still planning to review the second half of this patchset? :) At this point I reviewed more than half of the series :) Laurent, can you have a look at the upper half?
Le 09/02/2021 à 20:30, Mark Cave-Ayland a écrit : > The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to > and from the target. Since the SCSI bus is 16-bits wide, use the memory API > to split a 4 byte access into 2 x 2 byte accesses. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > hw/scsi/esp.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c > index 7671cc398d..1d56c99527 100644 > --- a/hw/scsi/esp.c > +++ b/hw/scsi/esp.c > @@ -1003,7 +1003,9 @@ static const MemoryRegionOps sysbus_esp_pdma_ops = { > .write = sysbus_esp_pdma_write, > .endianness = DEVICE_NATIVE_ENDIAN, > .valid.min_access_size = 1, > - .valid.max_access_size = 2, > + .valid.max_access_size = 4, > + .impl.min_access_size = 1, > + .impl.max_access_size = 2, > }; > > static const struct SCSIBusInfo esp_scsi_info = { > @@ -1048,7 +1050,7 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) > sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); > sysbus_init_mmio(sbd, &sysbus->iomem); > memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, > - sysbus, "esp-pdma", 2); > + sysbus, "esp-pdma", 4); > sysbus_init_mmio(sbd, &sysbus->pdma); > > qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); > Reviewed-by: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 7671cc398d..1d56c99527 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -1003,7 +1003,9 @@ static const MemoryRegionOps sysbus_esp_pdma_ops = { .write = sysbus_esp_pdma_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid.min_access_size = 1, - .valid.max_access_size = 2, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 2, }; static const struct SCSIBusInfo esp_scsi_info = { @@ -1048,7 +1050,7 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); sysbus_init_mmio(sbd, &sysbus->iomem); memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, - sysbus, "esp-pdma", 2); + sysbus, "esp-pdma", 4); sysbus_init_mmio(sbd, &sysbus->pdma); qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to and from the target. Since the SCSI bus is 16-bits wide, use the memory API to split a 4 byte access into 2 x 2 byte accesses. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)