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Wed, 27 Jan 2021 01:54:39 -0500 (EST) From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] hw/mips/malta: Use bootloader helper to set BAR resgiters Date: Wed, 27 Jan 2021 14:54:23 +0800 Message-Id: <20210127065424.114125-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210127065424.114125-1-jiaxun.yang@flygoat.com> References: <20210127065424.114125-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=66.111.4.224; envelope-from=jiaxun.yang@flygoat.com; helo=new2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Translate embedded assembly into IO writes which is more readable. Signed-off-by: Jiaxun Yang --- hw/mips/malta.c | 68 ++++++++++++++++--------------------------------- 1 file changed, 22 insertions(+), 46 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ffd67b8293..9466fd1058 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -875,55 +875,31 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, p = (uint32_t *) (base + 0x580); /* Load BAR registers as done by YAMON */ - stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ -#else - stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ -#endif - stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ - - stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ -#else - stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ -#endif - stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ -#else - stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ -#endif - stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ -#else - stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ -#endif - stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ -#else - stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ -#endif - stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ -#else - stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ -#endif - stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ + /* Bus endianess is always reversed */ #ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ +#define cpu_to_gt32 cpu_to_le32 #else - stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ +#define cpu_to_gt32 cpu_to_be32 #endif - stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ + bl_gen_write_u32(&p, cpu_to_gt32(0xdf000000), + cpu_mips_phys_to_kseg1(NULL, 0x14000068)); + /* setup MEM-to-PCI0 mapping */ + /* setup PCI0 io window to 0x18000000-0x181fffff */ + bl_gen_write_u32(&p, cpu_to_gt32(0xc0000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00048)); + bl_gen_write_u32(&p, cpu_to_gt32(0x40000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00050)); + /* setup PCI0 mem windows */ + bl_gen_write_u32(&p, cpu_to_gt32(0x80000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00058)); + bl_gen_write_u32(&p, cpu_to_gt32(0x3f000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00060)); + bl_gen_write_u32(&p, cpu_to_gt32(0xc1000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00080)); + bl_gen_write_u32(&p, cpu_to_gt32(0x5e000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00088)); +#undef cpu_to_gt32 if (semihosting_get_argc()) { a0 = 0;