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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y66sm7095961wmd.14.2020.10.12.08.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:37:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile Date: Mon, 12 Oct 2020 16:37:46 +0100 Message-Id: <20201012153746.9996-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153746.9996-1-peter.maydell@linaro.org> References: <20201012153746.9996-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile specific part of the sanitizing of the value to be written to the FPSCR used a mask which always zeroed bit 19, which is FZ16. This is incorrect when the CPU supports 16-bit floating point arithmetic, because the bit should be writeable. Code earlier in the function already handles making this bit be RES0 if the CPU doesn't implement the FP16 feature, so we can simply stop masking it out for M-profile. Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 350150adbf1..4b0bb2bacfb 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -198,13 +198,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) if (arm_feature(env, ARM_FEATURE_M)) { /* - * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits + * M profile FPSCR is RES0 for the QC, STRIDE, LEN bits * and also for the trapped-exception-handling bits IxE. * From v8.1M with the low-overhead-loop extension bits * [18:16] are used for LTPSIZE and (since we don't implement * MVE) always read as 4 and ignore writes. + * FZ16 has already been handled as RES0 above if needed. */ - val &= 0xf7c0009f; + val &= 0xf7c8009f; if (cpu_isar_feature(aa32_lob, cpu)) { val |= 4 << 16; }