| Message ID | 20200721133742.2298-2-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] target/riscv: Quiet Coverity complains about vamo* | expand |
On Tue, Jul 21, 2020 at 6:38 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Although not explicitly specified that the the destination > vector register groups cannot overlap the source vector register group, > it is still necessary. > > And this constraint has been added to the v0.8 spec. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index 7b4752b911..887c6b8883 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) > return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); > } > > +/* > + * For vector indexed segment loads, the destination vector register > + * groups cannot overlap the source vector register group (specified by > + * `vs2`), else an illegal instruction exception is raised. > + */ > static bool ld_index_check(DisasContext *s, arg_rnfvm* a) > { > return (vext_check_isa_ill(s) && > vext_check_overlap_mask(s, a->rd, a->vm, false) && > vext_check_reg(s, a->rd, false) && > vext_check_reg(s, a->rs2, false) && > - vext_check_nf(s, a->nf)); > + vext_check_nf(s, a->nf) && > + ((a->nf == 1) || > + vext_check_overlap_group(a->rd, a->nf << s->lmul, > + a->rs2, 1 << s->lmul))); > } > > GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) > -- > 2.23.0 > >
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 7b4752b911..887c6b8883 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } +/* + * For vector indexed segment loads, the destination vector register + * groups cannot overlap the source vector register group (specified by + * `vs2`), else an illegal instruction exception is raised. + */ static bool ld_index_check(DisasContext *s, arg_rnfvm* a) { return (vext_check_isa_ill(s) && vext_check_overlap_mask(s, a->rd, a->vm, false) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + vext_check_nf(s, a->nf) && + ((a->nf == 1) || + vext_check_overlap_group(a->rd, a->nf << s->lmul, + a->rs2, 1 << s->lmul))); } GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)