From patchwork Sat Jul 11 16:16:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1327353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B3wDv1Zssz9sRW for ; Sun, 12 Jul 2020 02:22:55 +1000 (AEST) Received: from localhost ([::1]:43410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIH6-0006Og-Tj for incoming@patchwork.ozlabs.org; Sat, 11 Jul 2020 12:22:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDX-0007cS-O5; Sat, 11 Jul 2020 12:19:11 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDV-0001M3-Ke; Sat, 11 Jul 2020 12:19:11 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1356943|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0178803-0.00146885-0.980651; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16384; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:42 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 09/11] riscv: Define riscv struct reginfo Date: Sun, 12 Jul 2020 00:16:53 +0800 Message-Id: <20200711161655.2856-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 0000000..4536480 --- /dev/null +++ b/risu_reginfo_riscv64.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(T-Head) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#ifndef RISU_REGINFO_RISCV64_H +#define RISU_REGINFO_RISCV64_H + +struct reginfo { + uint64_t fault_address; + uint64_t regs[32]; + uint64_t fregs[32]; + uint64_t pc; + uint32_t flags; + uint32_t faulting_insn; + + /* FP */ + uint32_t fcsr; +}; + +#endif /* RISU_REGINFO_RISCV64_H */