diff mbox series

[06/14] hw/display/cirrus_vga: Convert debug printf() to trace event

Message ID 20200526062252.19852-7-f4bug@amsat.org
State New
Headers show
Series hw/display: Omnibus cleanups | expand

Commit Message

Philippe Mathieu-Daudé May 26, 2020, 6:22 a.m. UTC
Convert the final bit of DEBUG_BITBLT to a tracepoint.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/display/cirrus_vga.c | 24 ++++++++++--------------
 hw/display/trace-events |  1 +
 2 files changed, 11 insertions(+), 14 deletions(-)

Comments

Alistair Francis May 26, 2020, 4:46 p.m. UTC | #1
On Mon, May 25, 2020 at 11:25 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Convert the final bit of DEBUG_BITBLT to a tracepoint.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/display/cirrus_vga.c | 24 ++++++++++--------------
>  hw/display/trace-events |  1 +
>  2 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
> index 76e2dc5bb6..92c197cdde 100644
> --- a/hw/display/cirrus_vga.c
> +++ b/hw/display/cirrus_vga.c
> @@ -53,7 +53,6 @@
>   */
>
>  //#define DEBUG_CIRRUS
> -//#define DEBUG_BITBLT
>
>  /***************************************
>   *
> @@ -950,19 +949,16 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
>      s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
>      s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
>
> -#ifdef DEBUG_BITBLT
> -    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
> -           blt_rop,
> -           s->cirrus_blt_mode,
> -           s->cirrus_blt_modeext,
> -           s->cirrus_blt_width,
> -           s->cirrus_blt_height,
> -           s->cirrus_blt_dstpitch,
> -           s->cirrus_blt_srcpitch,
> -           s->cirrus_blt_dstaddr,
> -           s->cirrus_blt_srcaddr,
> -           s->vga.gr[0x2f]);
> -#endif
> +    trace_vga_cirrus_bitblt_start(blt_rop,
> +                                  s->cirrus_blt_mode,
> +                                  s->cirrus_blt_modeext,
> +                                  s->cirrus_blt_width,
> +                                  s->cirrus_blt_height,
> +                                  s->cirrus_blt_dstpitch,
> +                                  s->cirrus_blt_srcpitch,
> +                                  s->cirrus_blt_dstaddr,
> +                                  s->cirrus_blt_srcaddr,
> +                                  s->vga.gr[0x2f]);
>
>      switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
>      case CIRRUS_BLTMODE_PIXELWIDTH8:
> diff --git a/hw/display/trace-events b/hw/display/trace-events
> index c3043e4ced..bb089a5f5e 100644
> --- a/hw/display/trace-events
> +++ b/hw/display/trace-events
> @@ -134,6 +134,7 @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
>  vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
>  vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
>  vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x"
> +vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x"
>
>  # sii9022.c
>  sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
> --
> 2.21.3
>
>
diff mbox series

Patch

diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index 76e2dc5bb6..92c197cdde 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -53,7 +53,6 @@ 
  */
 
 //#define DEBUG_CIRRUS
-//#define DEBUG_BITBLT
 
 /***************************************
  *
@@ -950,19 +949,16 @@  static void cirrus_bitblt_start(CirrusVGAState * s)
     s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
     s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
 
-#ifdef DEBUG_BITBLT
-    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
-           blt_rop,
-           s->cirrus_blt_mode,
-           s->cirrus_blt_modeext,
-           s->cirrus_blt_width,
-           s->cirrus_blt_height,
-           s->cirrus_blt_dstpitch,
-           s->cirrus_blt_srcpitch,
-           s->cirrus_blt_dstaddr,
-           s->cirrus_blt_srcaddr,
-           s->vga.gr[0x2f]);
-#endif
+    trace_vga_cirrus_bitblt_start(blt_rop,
+                                  s->cirrus_blt_mode,
+                                  s->cirrus_blt_modeext,
+                                  s->cirrus_blt_width,
+                                  s->cirrus_blt_height,
+                                  s->cirrus_blt_dstpitch,
+                                  s->cirrus_blt_srcpitch,
+                                  s->cirrus_blt_dstaddr,
+                                  s->cirrus_blt_srcaddr,
+                                  s->vga.gr[0x2f]);
 
     switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
     case CIRRUS_BLTMODE_PIXELWIDTH8:
diff --git a/hw/display/trace-events b/hw/display/trace-events
index c3043e4ced..bb089a5f5e 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -134,6 +134,7 @@  vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
 vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x"
+vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x"
 
 # sii9022.c
 sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"