diff mbox series

[PULL,02/38] target/riscv: Add the Hypervisor extension

Message ID	20200303004848.136788-3-palmerdabbelt@google.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Subject: [PULL 02/38] target/riscv: Add the Hypervisor extension Date: Mon, 2 Mar 2020 16:48:12 -0800 Message-Id: <20200303004848.136788-3-palmerdabbelt@google.com> In-Reply-To: <20200303004848.136788-1-palmerdabbelt@google.com> References: <20200303004848.136788-1-palmerdabbelt@google.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Chih-Min Chao <chihmin.chao@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Palmer Dabbelt <palmerdabbelt@google.com> From: Palmer Dabbelt <palmerdabbelt@google.com> To: Peter Maydell <peter.maydell@linaro.org> Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/38] target/riscv: Convert MIP CSR to target_ulong \| expand [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong [PULL,02/38] target/riscv: Add the Hypervisor extension [PULL,03/38] target/riscv: Add the Hypervisor CSRs to CPUState [PULL,04/38] target/riscv: Add support for the new execption numbers [PULL,05/38] target/riscv: Rename the H irqs to VS irqs [PULL,06/38] target/riscv: Add the virtulisation mode [PULL,07/38] target/riscv: Add the force HS exception mode [PULL,08/38] target/riscv: Fix CSR perm checking for HS mode [PULL,09/38] target/riscv: Print priv and virt in disas log [PULL,10/38] target/riscv: Dump Hypervisor registers if enabled [PULL,11/38] target/riscv: Add Hypervisor CSR access functions [PULL,12/38] target/riscv: Add Hypervisor virtual CSRs accesses [PULL,13/38] target/riscv: Add Hypervisor machine CSRs accesses [PULL,14/38] target/riscv: Add virtual register swapping function [PULL,15/38] target/riscv: Set VS bits in mideleg for Hyp extension [PULL,16/38] target/riscv: Extend the MIE CSR to support virtulisation [PULL,17/38] target/riscv: Extend the SIP CSR to support virtulisation [PULL,18/38] target/riscv: Add support for virtual interrupt setting [PULL,19/38] target/ricsv: Flush the TLB on virtulisation mode changes [PULL,20/38] target/riscv: Generate illegal instruction on WFI when V=1 [PULL,21/38] target/riscv: Add hypvervisor trap support [PULL,22/38] target/riscv: Add Hypervisor trap return support [PULL,23/38] target/riscv: Add hfence instructions [PULL,24/38] target/riscv: Remove the hret instruction [PULL,25/38] target/riscv: Only set TB flags with FP status if enabled [PULL,26/38] target/riscv: Disable guest FP support based on virtual status [PULL,27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty [PULL,28/38] target/riscv: Respect MPRV and SPRV for floating point ops [PULL,29/38] target/riscv: Allow specifying MMU stage [PULL,30/38] target/riscv: Implement second stage MMU [PULL,31/38] target/riscv: Raise the new execptions when 2nd stage translation fails [PULL,32/38] target/riscv: Set htval and mtval2 on execptions [PULL,33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR [PULL,34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [PULL,35/38] target/riscv: Allow enabling the Hypervisor extension [PULL,36/38] riscv: virt: Allow PCI address 0 [PULL,37/38] target/riscv: Emulate TIME CSRs for privileged mode [PULL,38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

Commit Message

Palmer Dabbelt March 3, 2020, 12:48 a.m. UTC

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@ 
 #define RVC RV('C')
 #define RVS RV('S')
 #define RVU RV('U')
+#define RVH RV('H')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there