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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition Date: Thu, 19 Dec 2019 19:51:16 +0100 Message-Id: <20191219185127.24388-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This controller is able to use up to 6 timers. Later we will reuse part of it to model other similar controllers but with less timers. To simplify the VMSTATE, we'll keep a max of 6 timers. Add a definition for that value. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --- include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------ hw/timer/allwinner-a10-pit.c | 8 ++++---- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 6aceda81ee..54c40c7db6 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -7,6 +7,8 @@ #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) +#define AW_PIT_TIMER_MAX 6 + #define AW_A10_PIT_TIMER_NR 6 #define AW_A10_PIT_TIMER_IRQ 0x1 #define AW_A10_PIT_WDOG_IRQ 0x100 @@ -47,17 +49,17 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_A10_PIT_TIMER_NR]; - ptimer_state * timer[AW_A10_PIT_TIMER_NR]; - AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; + qemu_irq irq[AW_PIT_TIMER_MAX]; + ptimer_state * timer[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_A10_PIT_TIMER_NR]; - uint32_t interval[AW_A10_PIT_TIMER_NR]; - uint32_t count[AW_A10_PIT_TIMER_NR]; + uint32_t control[AW_PIT_TIMER_MAX]; + uint32_t interval[AW_PIT_TIMER_MAX]; + uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 117e5c7bf8..b31a0bcd43 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit = { .fields = (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } };