diff mbox series

[02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition

Message ID 20191219185127.24388-3-f4bug@amsat.org
State New
Headers show
Series [01/13] hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition | expand

Commit Message

Philippe Mathieu-Daudé Dec. 19, 2019, 6:51 p.m. UTC
This controller is able to use up to 6 timers.
Later we will reuse part of it to model other similar controllers
but with less timers. To simplify the VMSTATE, we'll keep a max
of 6 timers. Add a definition for that value.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------
 hw/timer/allwinner-a10-pit.c         |  8 ++++----
 2 files changed, 12 insertions(+), 10 deletions(-)

Comments

Niek Linnenbank Dec. 20, 2019, 9:27 p.m. UTC | #1
On Thu, Dec 19, 2019 at 7:51 PM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:

> This controller is able to use up to 6 timers.
> Later we will reuse part of it to model other similar controllers
> but with less timers. To simplify the VMSTATE, we'll keep a max
> of 6 timers. Add a definition for that value.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------
>  hw/timer/allwinner-a10-pit.c         |  8 ++++----
>  2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/timer/allwinner-a10-pit.h
> b/include/hw/timer/allwinner-a10-pit.h
> index 6aceda81ee..54c40c7db6 100644
> --- a/include/hw/timer/allwinner-a10-pit.h
> +++ b/include/hw/timer/allwinner-a10-pit.h
> @@ -7,6 +7,8 @@
>  #define TYPE_AW_A10_PIT "allwinner-A10-timer"
>  #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj),
> TYPE_AW_A10_PIT)
>
> +#define AW_PIT_TIMER_MAX        6
> +
>  #define AW_A10_PIT_TIMER_NR    6
>  #define AW_A10_PIT_TIMER_IRQ   0x1
>  #define AW_A10_PIT_WDOG_IRQ    0x100
> @@ -47,17 +49,17 @@ struct AwA10PITState {
>      /*< private >*/
>      SysBusDevice parent_obj;
>      /*< public >*/
> -    qemu_irq irq[AW_A10_PIT_TIMER_NR];
> -    ptimer_state * timer[AW_A10_PIT_TIMER_NR];
> -    AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
> +    qemu_irq irq[AW_PIT_TIMER_MAX];
> +    ptimer_state * timer[AW_PIT_TIMER_MAX];
> +    AwA10TimerContext timer_context[AW_PIT_TIMER_MAX];
>      MemoryRegion iomem;
>      uint32_t clk_freq[4];
>
>      uint32_t irq_enable;
>      uint32_t irq_status;
> -    uint32_t control[AW_A10_PIT_TIMER_NR];
> -    uint32_t interval[AW_A10_PIT_TIMER_NR];
> -    uint32_t count[AW_A10_PIT_TIMER_NR];
> +    uint32_t control[AW_PIT_TIMER_MAX];
> +    uint32_t interval[AW_PIT_TIMER_MAX];
> +    uint32_t count[AW_PIT_TIMER_MAX];
>      uint32_t watch_dog_mode;
>      uint32_t watch_dog_control;
>      uint32_t count_lo;
> diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
> index 117e5c7bf8..b31a0bcd43 100644
> --- a/hw/timer/allwinner-a10-pit.c
> +++ b/hw/timer/allwinner-a10-pit.c
> @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit = {
>      .fields = (VMStateField[]) {
>          VMSTATE_UINT32(irq_enable, AwA10PITState),
>          VMSTATE_UINT32(irq_status, AwA10PITState),
> -        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
> -        VMSTATE_UINT32_ARRAY(interval, AwA10PITState,
> AW_A10_PIT_TIMER_NR),
> -        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
> +        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX),
> +        VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX),
> +        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX),
>          VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
>          VMSTATE_UINT32(watch_dog_control, AwA10PITState),
>          VMSTATE_UINT32(count_lo, AwA10PITState),
>          VMSTATE_UINT32(count_hi, AwA10PITState),
>          VMSTATE_UINT32(count_ctl, AwA10PITState),
> -        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
> +        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> --
> 2.21.0
>
> Looks good and works fine with -M orangepi-pc and -M cubieboard.

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
diff mbox series

Patch

diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h
index 6aceda81ee..54c40c7db6 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -7,6 +7,8 @@ 
 #define TYPE_AW_A10_PIT "allwinner-A10-timer"
 #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
 
+#define AW_PIT_TIMER_MAX        6
+
 #define AW_A10_PIT_TIMER_NR    6
 #define AW_A10_PIT_TIMER_IRQ   0x1
 #define AW_A10_PIT_WDOG_IRQ    0x100
@@ -47,17 +49,17 @@  struct AwA10PITState {
     /*< private >*/
     SysBusDevice parent_obj;
     /*< public >*/
-    qemu_irq irq[AW_A10_PIT_TIMER_NR];
-    ptimer_state * timer[AW_A10_PIT_TIMER_NR];
-    AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
+    qemu_irq irq[AW_PIT_TIMER_MAX];
+    ptimer_state * timer[AW_PIT_TIMER_MAX];
+    AwA10TimerContext timer_context[AW_PIT_TIMER_MAX];
     MemoryRegion iomem;
     uint32_t clk_freq[4];
 
     uint32_t irq_enable;
     uint32_t irq_status;
-    uint32_t control[AW_A10_PIT_TIMER_NR];
-    uint32_t interval[AW_A10_PIT_TIMER_NR];
-    uint32_t count[AW_A10_PIT_TIMER_NR];
+    uint32_t control[AW_PIT_TIMER_MAX];
+    uint32_t interval[AW_PIT_TIMER_MAX];
+    uint32_t count[AW_PIT_TIMER_MAX];
     uint32_t watch_dog_mode;
     uint32_t watch_dog_control;
     uint32_t count_lo;
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index 117e5c7bf8..b31a0bcd43 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -203,15 +203,15 @@  static const VMStateDescription vmstate_a10_pit = {
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(irq_enable, AwA10PITState),
         VMSTATE_UINT32(irq_status, AwA10PITState),
-        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
-        VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
-        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
+        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX),
+        VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX),
+        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX),
         VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
         VMSTATE_UINT32(watch_dog_control, AwA10PITState),
         VMSTATE_UINT32(count_lo, AwA10PITState),
         VMSTATE_UINT32(count_hi, AwA10PITState),
         VMSTATE_UINT32(count_ctl, AwA10PITState),
-        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
+        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX),
         VMSTATE_END_OF_LIST()
     }
 };