From patchwork Wed Sep 18 14:56:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1164051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46YPzp5Yxtz9sNw for ; Thu, 19 Sep 2019 02:08:54 +1000 (AEST) Received: from localhost ([::1]:60458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcVf-00043T-WC for incoming@patchwork.ozlabs.org; Wed, 18 Sep 2019 12:08:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49836) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAbsl-0007c7-Fu for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAbsk-00073n-4x for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:39 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:46276) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iAbsj-00073G-UP for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:38 -0400 Received: by mail-pl1-f194.google.com with SMTP id q24so93157plr.13 for ; Wed, 18 Sep 2019 08:28:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=dMC8KBUimeo1KaZM5SCh8e6L1Wsgzgt11zDiG6xpaww=; b=SeYNhL89my9AbJ5SZZI8D+WbL1E5pKgRg36OMvRaECOYn2lnjOnBgWD7BwsXt3srl1 U5RTLRwomMiWXDqf7lElMzoOFeue1NpPg1ae3WXHxe1eB9hrDZad9VxAIgiFGJUqEQK2 qeTyIxCdZB9jrpbJXNX652Z9LP1/vS7YKaZJJwTZK13hDAwKGy/Gu2HfIy90uM/ier/x fN5GrAT0FQd15RBngrOV6MlVQ10NTjRkBloUo0QhdtX7DD55KyIaZ32A05ZuNi6X5/Vq CPgI8x2BnB3RDOgfYuKKjahYffXPXL0JfFyzNdwgqWUhF8OUoJvlW3z0os8Llz5chXmQ QBsA== X-Gm-Message-State: APjAAAX8knlYKoIV0CH9eaqj4zm+KXFLOpvxX3wIrOvwyo2bgX4Ae/YL 2vA7mXlu0J1N2dT8a3l5OglNSg== X-Google-Smtp-Source: APXvYqz2MrhtG5Qm8HtUIz+1t6qoPKJKVpqum/r+LHQj/Vu1aujjvHOIFApVjsUiZIlP2VlyVhVwcg== X-Received: by 2002:a17:902:720a:: with SMTP id ba10mr4911393plb.328.1568820516781; Wed, 18 Sep 2019 08:28:36 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id v3sm2548724pfm.119.2019.09.18.08.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 08:28:36 -0700 (PDT) Date: Wed, 18 Sep 2019 07:56:29 -0700 Message-Id: <20190918145640.17349-38-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> References: <20190918145640.17349-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.194 Subject: [Qemu-devel] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Jonathan Behrens , Chih-Min Chao , Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 4 ++-- include/hw/riscv/sifive_u.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9e698a11c4..b66eaef607 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -62,8 +62,8 @@ static const struct MemmapEntry { [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index bb46745356..7dfd1cb22e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -65,8 +65,8 @@ enum { }; enum { - SIFIVE_U_UART0_IRQ = 3, - SIFIVE_U_UART1_IRQ = 4, + SIFIVE_U_UART0_IRQ = 4, + SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GEM_IRQ = 0x35 };