[PULL,35/47] riscv: sifive_u: Add PRCI block to the SoC

Message ID	20190910190513.21160-36-palmer@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Date: Tue, 10 Sep 2019 12:05:01 -0700 Message-Id: <20190910190513.21160-36-palmer@sifive.com> In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 \| expand [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 [PULL,02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart [PULL,03/47] riscv: sifive_u: Fix clock-names property for ethernet node [PULL,04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL,05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL,06/47] riscv: plic: Remove unused interrupt functions [PULL,07/47] target/riscv: Create function to test if FP is enabled [PULL,08/47] target/riscv: Update the Hypervisor CSRs to v0.4 [PULL,09/47] riscv: rv32: Root page table address can be larger than 32-bit [PULL,10/47] riscv: Add a helper routine for finding firmware [PULL,11/47] riscv: Resolve full path of the given bios image [PULL,12/47] riscv: hmp: Add a command to show virtual memory mappings [PULL,13/47] riscv: sifive_test: Add reset functionality [PULL,14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion [PULL,15/47] riscv: hw: Remove superfluous "linux, phandle" property [PULL,16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [PULL,17/47] riscv: hw: Remove not needed PLIC properties in device tree [PULL,18/47] riscv: hw: Change create_fdt() to return void [PULL,19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [PULL,20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [PULL,22/47] riscv: sifive_u: Remove the unnecessary include of prci header [PULL,23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [PULL,24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [PULL,25/47] riscv: sifive_e: prci: Update the PRCI register block size [PULL,26/47] riscv: sifive_e: Drop sifive_mmio_emulate() [PULL,27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [PULL,28/47] riscv: hart: Extract hart realize to a separate routine [PULL,29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array [PULL,30/47] riscv: sifive_u: Set the minimum number of cpus to 2 [PULL,31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [PULL,32/47] riscv: sifive_u: Update PLIC hart topology configuration string [PULL,33/47] riscv: sifive: Implement PRCI model for FU540 [PULL,34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes [PULL,35/47] riscv: sifive_u: Add PRCI block to the SoC [PULL,36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [PULL,37/47] riscv: sifive_u: Update UART base addresses and IRQs [PULL,38/47] riscv: sifive_u: Change UART node name in device tree [PULL,39/47] riscv: roms: Update default bios for sifive_u machine [PULL,40/47] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL,41/47] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL,42/47] riscv: sifive_u: Fix broken GEM support [PULL,43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL,44/47] riscv: sifive_u: Update model and compatible strings in device tree [PULL,45/47] target/riscv: Use both register name and ABI name [PULL,46/47] target/riscv: Fix mstatus dirty mask [PULL,47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

Message ID

20190910190513.21160-36-palmer@sifive.com

State

New

Headers

Date: Tue, 10 Sep 2019 12:05:01 -0700
Message-Id: <20190910190513.21160-36-palmer@sifive.com>
In-Reply-To: <20190910190513.21160-1-palmer@sifive.com>
References: <20190910190513.21160-1-palmer@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC
Precedence: list
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, 
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Palmer Dabbelt <palmer@sifive.com>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 | expand

Commit Message

Palmer Dabbelt Sept. 10, 2019, 7:05 p.m. UTC

From: Bin Meng <bmeng.cn@gmail.com>

Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/sifive_u.c         | 24 +++++++++++++++++++++++-
 include/hw/riscv/sifive_u.h |  3 +++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3ee6fcbd12..ff2e28e26c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -9,6 +9,7 @@ 
  * 0) UART
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
+ * 3) PRCI (Power, Reset, Clock, Interrupt)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -60,6 +61,7 @@  static const struct MemmapEntry {
     [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
+    [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
@@ -77,7 +79,7 @@  static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     uint32_t *cells;
     char *nodename;
     char ethclk_names[] = "pclk\0hclk\0tx_clk";
-    uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+    uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
     uint32_t uartclk_phandle;
     uint32_t hfclk_phandle, rtcclk_phandle;
 
@@ -188,6 +190,21 @@  static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(cells);
     g_free(nodename);
 
+    prci_phandle = phandle++;
+    nodename = g_strdup_printf("/soc/clock-controller@%lx",
+        (long)memmap[SIFIVE_U_PRCI].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
+    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
+    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+        hfclk_phandle, rtcclk_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+        0x0, memmap[SIFIVE_U_PRCI].base,
+        0x0, memmap[SIFIVE_U_PRCI].size);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+        "sifive,fu540-c000-prci");
+    g_free(nodename);
+
     plic_phandle = phandle++;
     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
@@ -402,6 +419,8 @@  static void riscv_sifive_u_soc_init(Object *obj)
     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 
+    sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
+                          TYPE_SIFIVE_U_PRCI);
     sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
                           TYPE_CADENCE_GEM);
 }
@@ -475,6 +494,9 @@  static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 
+    object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+
     for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
         plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
     }
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 24418145aa..bb46745356 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -22,6 +22,7 @@ 
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
+#include "hw/riscv/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -37,6 +38,7 @@  typedef struct SiFiveUSoCState {
     RISCVHartArrayState e_cpus;
     RISCVHartArrayState u_cpus;
     DeviceState *plic;
+    SiFiveUPRCIState prci;
     CadenceGEMState gem;
 } SiFiveUSoCState;
 
@@ -55,6 +57,7 @@  enum {
     SIFIVE_U_MROM,
     SIFIVE_U_CLINT,
     SIFIVE_U_PLIC,
+    SIFIVE_U_PRCI,
     SIFIVE_U_UART0,
     SIFIVE_U_UART1,
     SIFIVE_U_DRAM,