[PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs

From: Alistair Francis <Alistair.Francis@wdc.com>

Date: Sat, 25 May 2019 18:09:36 -0700
Message-Id: <20190526010948.3923-18-palmer@sifive.com>
In-Reply-To: <20190526010948.3923-1-palmer@sifive.com>
References: <20190526010948.3923-1-palmer@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no
	MMU CPUs
Precedence: list
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Message ID	20190526010948.3923-18-palmer@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Date: Sat, 25 May 2019 18:09:36 -0700 Message-Id: <20190526010948.3923-18-palmer@sifive.com> In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/29] SiFive RISC-V GPIO Device \| expand [PULL,01/29] SiFive RISC-V GPIO Device [PULL,02/29] target/riscv: Do not allow sfence.vma from user mode [PULL,03/29] RISC-V: fix single stepping over ret and other branching instructions [PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats [PULL,05/29] target/riscv: Use --static-decode for decodetree [PULL,06/29] target/riscv: Merge argument sets for insn32 and insn16 [PULL,07/29] target/riscv: Merge argument decode for RVC shifti [PULL,08/29] target/riscv: Use pattern groups in insn16.decode [PULL,09/29] target/riscv: Split RVC32 and RVC64 insns into separate files [PULL,10/29] target/riscv: Split gen_arith_imm into functional and temp [PULL,11/29] target/riscv: Remove spaces from register names [PULL,12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv [PULL,13/29] linux-user/riscv: Add the CPU type as a comment [PULL,14/29] riscv: virt: Allow specifying a CPU via commandline [PULL,15/29] target/riscv: Create settable CPU properties [PULL,16/29] target/riscv: Add a base 32 and 64 bit CPU [PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs [PULL,18/29] riscv: spike: Add a generic spike machine [PULL,19/29] target/riscv: Mark privilege level 2 as reserved [PULL,20/29] target/riscv: Trigger interrupt on MIP update asynchronously [PULL,21/29] target/riscv: Improve the scause logic [PULL,22/29] target/riscv: Add the MPV and MTL mstatus bits [PULL,23/29] target/riscv: Allow setting mstatus virtulisation bits [PULL,24/29] target/riscv: Add Hypervisor CSR macros [PULL,25/29] target/riscv: Add the HSTATUS register masks [PULL,26/29] target/riscv: Add the HGATP register masks [PULL,27/29] target/riscv: Add checks for several RVC reserved operands [PULL,28/29] target/riscv: More accurate handling of `sip` CSR [PULL,29/29] target/riscv: Only flush TLB if SATP.ASID changes

[PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs

Commit Message

Patch