[v3,05/10] hw/riscv: Replace global smp variables with machine smp properties

The global smp variables in riscv are replaced with smp machine properties.

A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
 hw/riscv/sifive_e.c    | 6 ++++--
 hw/riscv/sifive_plic.c | 3 +++
 hw/riscv/sifive_u.c    | 6 ++++--
 hw/riscv/spike.c       | 2 ++
 hw/riscv/virt.c        | 1 +
 5 files changed, 14 insertions(+), 4 deletions(-)

On Sun, May 19, 2019 at 5:56 AM Like Xu <like.xu@linux.intel.com> wrote:
>
> The global smp variables in riscv are replaced with smp machine properties.
>
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the context OR replace it on the spot if it's
> only used once. No semantic changes.
>
> Signed-off-by: Like Xu <like.xu@linux.intel.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_e.c    | 6 ++++--
>  hw/riscv/sifive_plic.c | 3 +++
>  hw/riscv/sifive_u.c    | 6 ++++--
>  hw/riscv/spike.c       | 2 ++
>  hw/riscv/virt.c        | 1 +
>  5 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index b1cd11363c..ae86a63c04 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -137,6 +137,7 @@ static void riscv_sifive_e_init(MachineState *machine)
>
>  static void riscv_sifive_e_soc_init(Object *obj)
>  {
> +    MachineState *ms = MACHINE(qdev_get_machine());
>      SiFiveESoCState *s = RISCV_E_SOC(obj);
>
>      object_initialize_child(obj, "cpus", &s->cpus,
> @@ -144,12 +145,13 @@ static void riscv_sifive_e_soc_init(Object *obj)
>                              &error_abort, NULL);
>      object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
> +    object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
>                              &error_abort);
>  }
>
>  static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
>  {
> +    MachineState *ms = MACHINE(qdev_get_machine());
>      const struct MemmapEntry *memmap = sifive_e_memmap;
>
>      SiFiveESoCState *s = RISCV_E_SOC(dev);
> @@ -179,7 +181,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
>          SIFIVE_E_PLIC_CONTEXT_STRIDE,
>          memmap[SIFIVE_E_PLIC].size);
>      sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> -        memmap[SIFIVE_E_CLINT].size, smp_cpus,
> +        memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
>          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
>      sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
>          memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index 07a032d93d..d4010a1f39 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -23,6 +23,7 @@
>  #include "qemu/error-report.h"
>  #include "hw/sysbus.h"
>  #include "hw/pci/msi.h"
> +#include "hw/boards.h"
>  #include "target/riscv/cpu.h"
>  #include "sysemu/sysemu.h"
>  #include "hw/riscv/sifive_plic.h"
> @@ -438,6 +439,8 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
>
>  static void sifive_plic_realize(DeviceState *dev, Error **errp)
>  {
> +    MachineState *ms = MACHINE(qdev_get_machine());
> +    unsigned int smp_cpus = ms->smp.cpus;
>      SiFivePLICState *plic = SIFIVE_PLIC(dev);
>      int i;
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 5ecc47cea3..43bf256946 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -321,13 +321,14 @@ static void riscv_sifive_u_init(MachineState *machine)
>
>  static void riscv_sifive_u_soc_init(Object *obj)
>  {
> +    MachineState *ms = MACHINE(qdev_get_machine());
>      SiFiveUSoCState *s = RISCV_U_SOC(obj);
>
>      object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
>                              TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
>      object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
> +    object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
>                              &error_abort);
>
>      sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> @@ -336,6 +337,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
>
>  static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>  {
> +    MachineState *ms = MACHINE(qdev_get_machine());
>      SiFiveUSoCState *s = RISCV_U_SOC(dev);
>      const struct MemmapEntry *memmap = sifive_u_memmap;
>      MemoryRegion *system_memory = get_system_memory();
> @@ -371,7 +373,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
>          serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
>      sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
> -        memmap[SIFIVE_U_CLINT].size, smp_cpus,
> +        memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
>          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
>
>      for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 2a000a5800..6a747ff22e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -171,6 +171,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
>      MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
>      int i;
> +    unsigned int smp_cpus = machine->smp.cpus;
>
>      /* Initialize SOC */
>      object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
> @@ -253,6 +254,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
>      MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
>      int i;
> +    unsigned int smp_cpus = machine->smp.cpus;
>
>      /* Initialize SOC */
>      object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index fc4c6b306e..b3f1962384 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -395,6 +395,7 @@ static void riscv_virt_board_init(MachineState *machine)
>      char *plic_hart_config;
>      size_t plic_hart_config_len;
>      int i;
> +    unsigned int smp_cpus = machine->smp.cpus;
>      void *fdt;
>
>      /* Initialize SOC */
> --
> 2.21.0
>

On Sun, May 19, 2019 at 04:54:23AM +0800, Like Xu wrote:
> The global smp variables in riscv are replaced with smp machine properties.
> 
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the context OR replace it on the spot if it's
> only used once. No semantic changes.
> 
> Signed-off-by: Like Xu <like.xu@linux.intel.com>
> ---
>  hw/riscv/sifive_e.c    | 6 ++++--
>  hw/riscv/sifive_plic.c | 3 +++
>  hw/riscv/sifive_u.c    | 6 ++++--
>  hw/riscv/spike.c       | 2 ++
>  hw/riscv/virt.c        | 1 +
>  5 files changed, 14 insertions(+), 4 deletions(-)

This was incomplete, I had to apply the following fixup.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 hw/riscv/spike.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 9e95f2c13c..d91d49dcae 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -172,6 +172,7 @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     int i;
+    unsigned int smp_cpus = machine->smp.cpus;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),

On 2019/6/20 22:52, Eduardo Habkost wrote:
> On Sun, May 19, 2019 at 04:54:23AM +0800, Like Xu wrote:
>> The global smp variables in riscv are replaced with smp machine properties.
>>
>> A local variable of the same name would be introduced in the declaration
>> phase if it's used widely in the context OR replace it on the spot if it's
>> only used once. No semantic changes.
>>
>> Signed-off-by: Like Xu <like.xu@linux.intel.com>
>> ---
>>   hw/riscv/sifive_e.c    | 6 ++++--
>>   hw/riscv/sifive_plic.c | 3 +++
>>   hw/riscv/sifive_u.c    | 6 ++++--
>>   hw/riscv/spike.c       | 2 ++
>>   hw/riscv/virt.c        | 1 +
>>   5 files changed, 14 insertions(+), 4 deletions(-)
> 
> This was incomplete, I had to apply the following fixup.
> 
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Reviewed-by: Like Xu <like.xu@linux.intel.com>

> ---
>   hw/riscv/spike.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 9e95f2c13c..d91d49dcae 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -172,6 +172,7 @@ static void spike_board_init(MachineState *machine)
>       MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>       MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
>       int i;
> +    unsigned int smp_cpus = machine->smp.cpus;
>   
>       /* Initialize SOC */
>       object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
>