From patchwork Fri Mar 1 21:49:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1050468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="cK0eyAhx"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44B35V125cz9s7h for ; Sat, 2 Mar 2019 08:51:08 +1100 (AEDT) Received: from localhost ([127.0.0.1]:44538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzq3e-0002kH-Ky for incoming@patchwork.ozlabs.org; Fri, 01 Mar 2019 16:51:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzq2g-0002go-U0 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzq2e-0001kg-UE for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:06 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:39422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzq2d-0001c2-Q8 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:04 -0500 Received: by mail-pf1-x42a.google.com with SMTP id i20so12018264pfo.6 for ; Fri, 01 Mar 2019 13:50:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=IHFRb/uohgXvKCA9RSkbhFxt1pQb102pHlM16Aca788=; b=cK0eyAhxnLbJWuEUiLH+gavd+ahXKQeLJg++i18jdNDHPvgBWERDZDErXbZZidtIRR Zmp9QNXXYUE5td7wetLenQIGRYNvlrGf8LcOS7ogIcygVfEK+MlElU0jJVmQE2HY398M uGFtZnRWcpWMX9MoxC0ZNmilUGC8dav779322/k3GzxsVZ2EmOVqsfmk5gM9BuVuOy4c UPMzGNZlwdXcVvu1sn5rLPu4OeDSjhPLzCC47ZoVvMdVA5A/8HdGkHT1XwDKlMwmhug4 XK98Q/nKfc+8eLx9OaAyqIZPCTew6J7M0ByQALYaOXNhvBq9y4Ag1ViDe626oFSBK6a8 kjzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=IHFRb/uohgXvKCA9RSkbhFxt1pQb102pHlM16Aca788=; b=PhpJSw/7vBPDzR8APNcvbdK0tYNkn/ODRFEJy9KuvS8ft6DcQO4s9rAsXSReyIvzui YwzDzf7BG6hZZSgZfH0Tsf7hAHANWcckDDTDFPI+pYK3dNSYoIsyBvv3ESTVo75+/Byo 88YiMbkJGMp3PB+pUQiZT0tmnVxtLgZDpPKBagHi3OoJTQ3D1rwuLzFGOCHyapwtJjOE +xE5Bpwj2EUeHLgfNpqo+Hc2iDKVJxtEYOh/xzyImKnDTVhiAjONYuSzJKmxdgEuOt6r yP9NtsShUiQ3uIasNRa/rGPv6qip8HYW9TyBLwRje853JtX46n4fbPd2XEJV+/njMvhQ Wdbw== X-Gm-Message-State: AHQUAuYeHJ9LQGkI83m+bVNwzcyhLmno4VwgEeMr19NXDnU8jAaAq4Bz jKolR9P+XaFudws8tNXk94HiSjfzBK4= X-Google-Smtp-Source: AHgI3IY3hWMEto6DL2pMpeUfpBgWNZ59DpgC7BfGe/ILWInBrqLKOc1BR5FP4FCPZkMfjgIF2ov+Yg== X-Received: by 2002:aa7:83cb:: with SMTP id j11mr7878618pfn.117.1551476999830; Fri, 01 Mar 2019 13:49:59 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id j4sm30205916pfn.132.2019.03.01.13.49.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Mar 2019 13:49:59 -0800 (PST) Date: Fri, 1 Mar 2019 13:49:13 -0800 Message-Id: <20190301214945.4353-3-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190301214945.4353-1-palmer@sifive.com> References: <20190301214945.4353-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 19 ++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++ target/riscv/translate.c | 12 +----- 3 files changed, 69 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 44d4e922b6fa..81f56c16b45f 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,14 +17,33 @@ # this program. If not, see . # Fields: +%rs2 20:5 +%rs1 15:5 %rd 7:5 # immediates: +%imm_i 20:s12 +%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 +%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 %imm_u 12:s20 !function=ex_shift_12 +# Argument sets: +&b imm rs2 rs1 + # Formats 32: +@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd +@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd +@j .................... ..... ....... imm=%imm_j %rd # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u +jal .................... ..... 1101111 @j +jalr ............ ..... 000 ..... 1100111 @i +beq ....... ..... ..... 000 ..... 1100011 @b +bne ....... ..... ..... 001 ..... 1100011 @b +blt ....... ..... ..... 100 ..... 1100011 @b +bge ....... ..... ..... 101 ..... 1100011 @b +bltu ....... ..... ..... 110 ..... 1100011 @b +bgeu ....... ..... ..... 111 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 9885a8d27551..bcf20def50eb 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a) } return true; } + +static bool trans_jal(DisasContext *ctx, arg_jal *a) +{ + gen_jal(ctx, a->rd, a->imm); + return true; +} + +static bool trans_jalr(DisasContext *ctx, arg_jalr *a) +{ + gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_beq(DisasContext *ctx, arg_beq *a) +{ + gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bne(DisasContext *ctx, arg_bne *a) +{ + gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_blt(DisasContext *ctx, arg_blt *a) +{ + gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bge(DisasContext *ctx, arg_bge *a) +{ + gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bltu(DisasContext *ctx, arg_bltu *a) +{ + gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) +{ + + gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a273ac827448..fb284a5e08d6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1879,6 +1879,7 @@ static void decode_RV32_64C(DisasContext *ctx) { \ return imm << amount; \ } +EX_SH(1) EX_SH(12) bool decode_insn32(DisasContext *ctx, uint32_t insn); @@ -1907,17 +1908,6 @@ static void decode_RV32_64G(DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_JAL: - imm = GET_JAL_IMM(ctx->opcode); - gen_jal(ctx, rd, imm); - break; - case OPC_RISC_JALR: - gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_BRANCH: - gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, - GET_B_IMM(ctx->opcode)); - break; case OPC_RISC_LOAD: gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); break;