From patchwork Fri Feb 22 14:10:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 1046919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mail.uni-paderborn.de Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 445Z8l086lz9s2R for ; Sat, 23 Feb 2019 01:53:27 +1100 (AEDT) Received: from localhost ([127.0.0.1]:52056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxCCa-0003b0-LN for incoming@patchwork.ozlabs.org; Fri, 22 Feb 2019 09:53:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxBZo-0006VA-Ly for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:13:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxBZh-0000t4-KS for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:13:16 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:56046) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gxBZH-0006yx-51; Fri, 22 Feb 2019 09:12:52 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1gxBYF-0001kO-Go; Fri, 22 Feb 2019 15:11:43 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3163441-3; Fri, 22 Feb 2019 14:11:42 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:12 +0100 Message-Id: <20190222141024.22217-23-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140315, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.19.5580002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- target/riscv/translate.c | 8 +++++--- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index cc361ed4d1..5a09c6335a 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } -static bool trans_sb(DisasContext *ctx, arg_sb *a) +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) { - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + gen_get_gpr(dat, a->rs2); + + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); + tcg_temp_free(t0); + tcg_temp_free(dat); return true; } + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + return gen_store(ctx, a, MO_SB); +} + static bool trans_sh(DisasContext *ctx, arg_sh *a) { - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESW); } static bool trans_sw(DisasContext *ctx, arg_sw *a) { - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESL); } #ifdef TARGET_RISCV64 @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) static bool trans_sd(DisasContext *ctx, arg_sd *a) { - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TEQ); } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 99d6d3b4ae..cdc08b1bff 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { int frm; } DisasContext; +#ifdef TARGET_RISCV64 /* convert riscv funct3 to qemu memop for load/store */ static const int tcg_memop_lookup[8] = { [0 ... 7] = -1, @@ -69,6 +70,7 @@ static const int tcg_memop_lookup[8] = { [6] = MO_TEUL, #endif }; +#endif #ifdef TARGET_RISCV64 #define CASE_OP_32_64(X) case X: case glue(X, W) @@ -551,9 +553,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } -#endif -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) { TCGv t0 = tcg_temp_new(); @@ -572,6 +573,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(t0); tcg_temp_free(dat); } +#endif #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: @@ -736,7 +738,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, GET_C_LD_IMM(ctx->opcode)); #else /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/