From patchwork Thu Jan 31 07:32:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Zhong X-Patchwork-Id: 1033975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43qsf20f2Pz9s9h for ; Thu, 31 Jan 2019 18:42:50 +1100 (AEDT) Received: from localhost ([127.0.0.1]:50190 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gp6zo-0005AT-46 for incoming@patchwork.ozlabs.org; Thu, 31 Jan 2019 02:42:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gp6r5-0006mO-Qy for qemu-devel@nongnu.org; Thu, 31 Jan 2019 02:33:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gp6r4-00032v-F9 for qemu-devel@nongnu.org; Thu, 31 Jan 2019 02:33:47 -0500 Received: from mga07.intel.com ([134.134.136.100]:60061) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gp6r1-0002Yq-4x for qemu-devel@nongnu.org; Thu, 31 Jan 2019 02:33:45 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jan 2019 23:33:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,543,1539673200"; d="scan'208";a="112549032" Received: from he.bj.intel.com ([10.238.157.85]) by orsmga006.jf.intel.com with ESMTP; 30 Jan 2019 23:33:13 -0800 From: Yang Zhong To: qemu-devel@nongnu.org Date: Thu, 31 Jan 2019 15:32:25 +0800 Message-Id: <20190131073234.18037-19-yang.zhong@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190131073234.18037-1-yang.zhong@intel.com> References: <20190131073234.18037-1-yang.zhong@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 Subject: [Qemu-devel] [PATCH v1 18/27] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, pbonzini@redhat.com, thuth@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add the new configs to default-configs/riscv*-sofmmu.mak. Signed-off-by: Yang Zhong Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis Reviewed-by: Thomas Huth --- default-configs/riscv32-softmmu.mak | 7 +++++++ default-configs/riscv64-softmmu.mak | 7 +++++++ hw/riscv/Makefile.objs | 22 +++++++++++----------- 3 files changed, 25 insertions(+), 11 deletions(-) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index fbfd1d4e4b..65337166e1 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y CONFIG_VGA=y CONFIG_VGA_PCI=y + +CONFIG_SPIKE=y +CONFIG_HART=y +CONFIG_SIFIVE_E=y +CONFIG_SIFIVE=y +CONFIG_SIFIVE_U=y +CONFIG_RISCV_VIRT=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index fbfd1d4e4b..65337166e1 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y CONFIG_VGA=y CONFIG_VGA_PCI=y + +CONFIG_SPIKE=y +CONFIG_HART=y +CONFIG_SIFIVE_E=y +CONFIG_SIFIVE=y +CONFIG_SIFIVE_U=y +CONFIG_RISCV_VIRT=y diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index 1dde01d39d..79bfb3abf9 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -1,11 +1,11 @@ -obj-y += riscv_htif.o -obj-y += riscv_hart.o -obj-y += sifive_e.o -obj-y += sifive_clint.o -obj-y += sifive_prci.o -obj-y += sifive_plic.o -obj-y += sifive_test.o -obj-y += sifive_u.o -obj-y += sifive_uart.o -obj-y += spike.o -obj-y += virt.o +obj-$(CONFIG_SPIKE) += riscv_htif.o +obj-$(CONFIG_HART) += riscv_hart.o +obj-$(CONFIG_SIFIVE_E) += sifive_e.o +obj-$(CONFIG_SIFIVE) += sifive_clint.o +obj-$(CONFIG_SIFIVE) += sifive_prci.o +obj-$(CONFIG_SIFIVE) += sifive_plic.o +obj-$(CONFIG_SIFIVE) += sifive_test.o +obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE) += sifive_uart.o +obj-$(CONFIG_SPIKE) += spike.o +obj-$(CONFIG_RISCV_VIRT) += virt.o