From patchwork Fri Oct 19 01:56:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 986466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ur3D5KVO"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42bpvN6XDkz9sBq for ; Fri, 19 Oct 2018 12:57:20 +1100 (AEDT) Received: from localhost ([::1]:46221 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK2Q-0006WW-Fo for incoming@patchwork.ozlabs.org; Thu, 18 Oct 2018 21:57:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK1m-0006Ur-J9 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDK1i-0003w0-Fi for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:38 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46180) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDK1h-0003mk-N2 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:34 -0400 Received: by mail-pg1-x541.google.com with SMTP id r190-v6so3425915pgr.13 for ; Thu, 18 Oct 2018 18:56:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TTyR7xzj+PHD0K1CpzmCfsJOcm4+gyZaOYvrOzDqHOk=; b=Ur3D5KVOArDHnTltp5LUYGWt/ZgIi4veW0Z/25r99dmNsARdzSXsivr/7hPOZvmcod 8MIsMOAGSlsxszHGMKrvL+e457nG94IGEs9l7cAiMYojO51ahUBCPEssAxw1fk8IezCF kX/MXTdkaZxuJT3VwFXrIG9je/WCQt9dhlsjM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TTyR7xzj+PHD0K1CpzmCfsJOcm4+gyZaOYvrOzDqHOk=; b=ED1CSg7n2oKzELxuDaMzBlRlRgUnAgab8prl8i4OqE8Z7FnaAxAtzXD26iqWEyiCLr YOQ7pIOTZS0F7+ilgcf89jCs/raYsz08/K5ExnDgHEhWN0EfbLL/wMqM3m8AXZBjOE6Z j9jMwteEiHq8CH7MNr53+IBrwR67USXKI4NSBQZbpAeOJY9GScwfBft8m42oZEE57PVU 2bZzMvV3qc3ClXHe5RJsvIAVkQmwFwKJAB3L27Xy3z6ZrD/HvBPzVA0YaAaBXzGFS2li Tum8o2HfpH5ECpIa4aagxuLwmvQ2TIGskB4xU5LlZxI5RliKBijEu0Khky9L3L9uWISE S5hw== X-Gm-Message-State: ABuFfogV4AGJSkZmROjFp7hTr/M6fbMvJWL+44a6iTY/C3CSnipOLp9X RZCXEpzRbL2IYltuS/9jspZxwczvLHE= X-Google-Smtp-Source: ACcGV60pmkqMOZK9TLSlj88QcVU80US8NNA7E/wybM4DmgIOw1T7bZkpOSwOuqIWXzyQpTr92onetQ== X-Received: by 2002:a65:4783:: with SMTP id e3-v6mr30119517pgs.12.1539914184460; Thu, 18 Oct 2018 18:56:24 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id p62-v6sm33170892pfp.111.2018.10.18.18.56.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 18:56:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 18:56:17 -0700 Message-Id: <20181019015617.22583-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019015617.22583-1-richard.henderson@linaro.org> References: <20181019015617.22583-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Only the EL0 and EL1 TLBs are affected by the EL1 register, so flush only 2 of the 8 TLBs. In testing a boot of the Ubuntu installer to the first menu, this accounts for nearly all of the full tlb flushes: all but 11k of the 1.2M instances without the patch. Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed70ac645e..3ba8e66487 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2706,14 +2706,16 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, tcr->raw_tcr = value; } -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { ARMCPU *cpu = arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); + tlb_flush_by_mmuidx(CPU(cpu), + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } raw_write(env, ri, value); } @@ -2761,12 +2763,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .access = PL1_RW, .writefn = vmsa_ttbr_el1_write, .resetvalue = 0, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .access = PL1_RW, .writefn = vmsa_ttbr_el1_write, .resetvalue = 0, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, @@ -3018,12 +3020,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_el1_write, }, { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_el1_write, }, REGINFO_SENTINEL };