diff mbox series

[v2,1/2] target/xtensa: convert to do_transaction_failed

Message ID 20180829011652.4466-2-jcmvbkbc@gmail.com
State New
Headers show
Series target/xtensa: convert to do_transaction_failed | expand

Commit Message

Max Filippov Aug. 29, 2018, 1:16 a.m. UTC 
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v1->v2:
- change ldl_phys to address_space_ldl in get_pte and check transaction
  for success;

 target/xtensa/cpu.c       |  2 +-
 target/xtensa/cpu.h       |  7 ++++---
 target/xtensa/helper.c    | 22 +++++++++++++++++++---
 target/xtensa/op_helper.c | 12 +++++++-----
 4 files changed, 31 insertions(+), 12 deletions(-)

Comments

Peter Maydell Sept. 17, 2018, 4:54 p.m. UTC | #1 
On 29 August 2018 at 02:16, Max Filippov <jcmvbkbc@gmail.com> wrote:
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
> Changes v1->v2:
> - change ldl_phys to address_space_ldl in get_pte and check transaction
>   for success;

> --- a/target/xtensa/helper.c
> +++ b/target/xtensa/helper.c
> @@ -642,11 +642,27 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
>      int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
>              &paddr, &page_size, &access, false);
>
> -    qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
> -                  __func__, vaddr, ret ? ~0 : paddr);
> +    if (ret == 0) {
> +        qemu_log_mask(CPU_LOG_MMU,
> +                      "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
> +                      __func__, vaddr, pt_vaddr, paddr);
> +    } else {
> +        qemu_log_mask(CPU_LOG_MMU,
> +                      "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
> +                      __func__, vaddr, pt_vaddr, ret);
> +    }
>
>      if (ret == 0) {
> -        *pte = ldl_phys(cs->as, paddr);
> +        MemTxResult result;
> +
> +        *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
> +                                 &result);
> +        if (result != MEMTX_OK) {
> +            qemu_log_mask(CPU_LOG_MMU,
> +                          "%s: couldn't load PTE: transaction failed (%u)\n",
> +                          __func__, (unsigned)result);
> +            ret = 1;
> +        }

I don't know xtensa, but it seems a bit odd that this function now returns:
 * 0 on success
 * an exception cause code as returned from get_physical_addr_mmu() if
   that fails
 * 1, if the physical load fails

The callsite seems to only care about 0 or not-0, but it feels like
it might be cleaner to have it either return an exception code cause
in all cases, or just return a bool ?

>      }
>      return ret;
>  }

But that's a small nit, and the patch looks good overall, so
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 590813d4f7b9..a54dbe42602d 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -186,7 +186,7 @@  static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 #else
     cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
     cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
-    cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
+    cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
 #endif
     cc->debug_excp_handler = xtensa_breakpoint_handler;
     cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 7472cf3ca32a..1362772617ea 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -497,9 +497,10 @@  int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
                                 int mmu_idx);
 void xtensa_cpu_do_interrupt(CPUState *cpu);
 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
-void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
-                                     bool is_write, bool is_exec, int opaque,
-                                     unsigned size);
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+                                      unsigned size, MMUAccessType access_type,
+                                      int mmu_idx, MemTxAttrs attrs,
+                                      MemTxResult response, uintptr_t retaddr);
 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
                            fprintf_function cpu_fprintf, int flags);
 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f74636f67854..0484f5fab808 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -642,11 +642,27 @@  static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
             &paddr, &page_size, &access, false);
 
-    qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
-                  __func__, vaddr, ret ? ~0 : paddr);
+    if (ret == 0) {
+        qemu_log_mask(CPU_LOG_MMU,
+                      "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
+                      __func__, vaddr, pt_vaddr, paddr);
+    } else {
+        qemu_log_mask(CPU_LOG_MMU,
+                      "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
+                      __func__, vaddr, pt_vaddr, ret);
+    }
 
     if (ret == 0) {
-        *pte = ldl_phys(cs->as, paddr);
+        MemTxResult result;
+
+        *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
+                                 &result);
+        if (result != MEMTX_OK) {
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s: couldn't load PTE: transaction failed (%u)\n",
+                          __func__, (unsigned)result);
+            ret = 1;
+        }
     }
     return ret;
 }
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index d4c942d87980..06fe346f02ff 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -78,18 +78,20 @@  void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
     }
 }
 
-void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
-                                     bool is_write, bool is_exec, int opaque,
-                                     unsigned size)
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+                                      unsigned size, MMUAccessType access_type,
+                                      int mmu_idx, MemTxAttrs attrs,
+                                      MemTxResult response, uintptr_t retaddr)
 {
     XtensaCPU *cpu = XTENSA_CPU(cs);
     CPUXtensaState *env = &cpu->env;
 
+    cpu_restore_state(cs, retaddr, true);
     HELPER(exception_cause_vaddr)(env, env->pc,
-                                  is_exec ?
+                                  access_type == MMU_INST_FETCH ?
                                   INSTR_PIF_ADDR_ERROR_CAUSE :
                                   LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
-                                  is_exec ? addr : cs->mem_io_vaddr);
+                                  addr);
 }
 
 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)