Message ID | 20180710160013.26559-4-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
Series | accel/tcg: Support execution from MMIO and small MMU regions | expand |
On 07/10/2018 09:00 AM, Peter Maydell wrote: > When we support execution from non-RAM MMIO regions, get_page_addr_code() > will return -1 to indicate that there is no RAM at the requested address. > Handle this in tb_check_watchpoint() -- if the exception happened for a > PC which doesn't correspond to RAM then there is no need to invalidate > any TBs, because the one-instruction TB will not have been cached. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > accel/tcg/translate-all.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 49d77fad44e..d18018fa99d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2121,7 +2121,9 @@ void tb_check_watchpoint(CPUState *cpu) cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); addr = get_page_addr_code(env, pc); - tb_invalidate_phys_range(addr, addr + 1); + if (addr != -1) { + tb_invalidate_phys_range(addr, addr + 1); + } } }
When we support execution from non-RAM MMIO regions, get_page_addr_code() will return -1 to indicate that there is no RAM at the requested address. Handle this in tb_check_watchpoint() -- if the exception happened for a PC which doesn't correspond to RAM then there is no need to invalidate any TBs, because the one-instruction TB will not have been cached. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- accel/tcg/translate-all.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)