| Message ID | 20180316155340.25734-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: fix cpu_io_recompile | expand |
On 03/16/2018 04:53 PM, Richard Henderson wrote: > We have confused the number of instructions that have been > executed in the TB with the number of instructions needed > to repeat the I/O instruction. > > We have used cpu_restore_state_from_tb, which means that > the guest pc is pointing to the I/O instruction. The only > time the answer to the later question is not 1 is when > MIPS or SH4 need to re-execute the branch for the delay > slot as well. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > accel/tcg/translate-all.c | 21 ++++++++------------- > 1 file changed, 8 insertions(+), 13 deletions(-) > > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c > index 67795cd78c..d4190602d1 100644 > --- a/accel/tcg/translate-all.c > +++ b/accel/tcg/translate-all.c > @@ -1736,37 +1736,32 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) > cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", > (void *)retaddr); > } > - n = cpu->icount_decr.u16.low + tb->icount; > cpu_restore_state_from_tb(cpu, tb, retaddr); > - /* Calculate how many instructions had been executed before the fault > - occurred. */ > - n = n - cpu->icount_decr.u16.low; > - /* Generate a new TB ending on the I/O insn. */ > - n++; > + > /* On MIPS and SH, delay slot instructions can only be restarted if > they were already the first instruction in the TB. If this is not > the first instruction in a TB then re-execute the preceding > branch. */ > + n = 1; > #if defined(TARGET_MIPS) > - if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { > + if ((env->hflags & MIPS_HFLAG_BMASK) != 0 > + && env->active_tc.PC != tb->pc) { > env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); > cpu->icount_decr.u16.low++; > env->hflags &= ~MIPS_HFLAG_BMASK; > + n = 2; > } > #elif defined(TARGET_SH4) > if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 > - && n > 1) { > + && env->pc != tb->pc) { > env->pc -= 2; > cpu->icount_decr.u16.low++; > env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); > + n = 2; > } > #endif > - /* This should never happen. */ > - if (n > CF_COUNT_MASK) { > - cpu_abort(cpu, "TB too big during recompile"); > - } > > - /* Adjust the execution state of the next TB. */ > + /* Generate a new TB executing the I/O insn. */ > cpu->cflags_next_tb = curr_cflags() | CF_LAST_IO | n; > > if (tb->cflags & CF_NOCACHE) { >
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 67795cd78c..d4190602d1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1736,37 +1736,32 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } - n = cpu->icount_decr.u16.low + tb->icount; cpu_restore_state_from_tb(cpu, tb, retaddr); - /* Calculate how many instructions had been executed before the fault - occurred. */ - n = n - cpu->icount_decr.u16.low; - /* Generate a new TB ending on the I/O insn. */ - n++; + /* On MIPS and SH, delay slot instructions can only be restarted if they were already the first instruction in the TB. If this is not the first instruction in a TB then re-execute the preceding branch. */ + n = 1; #if defined(TARGET_MIPS) - if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { + if ((env->hflags & MIPS_HFLAG_BMASK) != 0 + && env->active_tc.PC != tb->pc) { env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); cpu->icount_decr.u16.low++; env->hflags &= ~MIPS_HFLAG_BMASK; + n = 2; } #elif defined(TARGET_SH4) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 - && n > 1) { + && env->pc != tb->pc) { env->pc -= 2; cpu->icount_decr.u16.low++; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); + n = 2; } #endif - /* This should never happen. */ - if (n > CF_COUNT_MASK) { - cpu_abort(cpu, "TB too big during recompile"); - } - /* Adjust the execution state of the next TB. */ + /* Generate a new TB executing the I/O insn. */ cpu->cflags_next_tb = curr_cflags() | CF_LAST_IO | n; if (tb->cflags & CF_NOCACHE) {
We have confused the number of instructions that have been executed in the TB with the number of instructions needed to repeat the I/O instruction. We have used cpu_restore_state_from_tb, which means that the guest pc is pointing to the I/O instruction. The only time the answer to the later question is not 1 is when MIPS or SH4 need to re-execute the branch for the delay slot as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- accel/tcg/translate-all.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-)