From patchwork Tue Jul 18 21:50:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 790616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xBv9B5NtYz9sNw for ; Wed, 19 Jul 2017 07:55:26 +1000 (AEST) Received: from localhost ([::1]:58755 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaSi-0008HK-Cw for incoming@patchwork.ozlabs.org; Tue, 18 Jul 2017 17:55:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaPj-0005hO-15 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXaPh-0003xT-Ob for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:19 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:48494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXaOY-0003VC-3w for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:17 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dXaOS-0000K2-5q; Tue, 18 Jul 2017 23:51:00 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dXaOO-000115-DO; Tue, 18 Jul 2017 23:50:56 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 23:50:20 +0200 Message-Id: <20170718215050.3812-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170718215050.3812-1-aurelien@aurel32.net> References: <20170718215050.3812-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 01/31] target/sh4: do not check for PR bit for fabs instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/sh4/helper.h | 2 -- target/sh4/op_helper.c | 10 ---------- target/sh4/translate.c | 15 +++------------ 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index dce859caea..f715224822 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -16,8 +16,6 @@ DEF_HELPER_3(macw, void, env, i32, i32) DEF_HELPER_2(ld_fpscr, void, env, i32) -DEF_HELPER_FLAGS_1(fabs_FT, TCG_CALL_NO_RWG_SE, f32, f32) -DEF_HELPER_FLAGS_1(fabs_DT, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 528a40ac1d..5e3a3ba68c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -252,16 +252,6 @@ static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) } } -float32 helper_fabs_FT(float32 t0) -{ - return float32_abs(t0); -} - -float64 helper_fabs_DT(float64 t0) -{ - return float64_abs(t0); -} - float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) { set_float_exception_flags(0, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8bc132b27b..bff212a78e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1695,19 +1695,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); } return; - case 0xf05d: /* fabs FRn/DRn */ + case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED - if (ctx->tbflags & FPSCR_PR) { - if (ctx->opcode & 0x0100) - break; /* illegal instruction */ - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); - gen_helper_fabs_DT(fp, fp); - gen_store_fpr64(fp, DREG(B11_8)); - tcg_temp_free_i64(fp); - } else { - gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); - } + tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], + 0x7fffffff); return; case 0xf06d: /* fsqrt FRn */ CHECK_FPU_ENABLED