From patchwork Sun Apr 23 22:32:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 753987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wB44T2GBdz9s1h for ; Mon, 24 Apr 2017 08:33:10 +1000 (AEST) Received: from localhost ([::1]:40799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2Q40-0006DR-Gx for incoming@patchwork.ozlabs.org; Sun, 23 Apr 2017 18:33:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53052) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2Q3R-0006D6-62 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:32:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2Q3Q-000587-4a for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:32:29 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:45504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d2Q3P-00057l-Uy for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:32:28 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d2Q3O-0002XP-S5; Mon, 24 Apr 2017 00:32:26 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d2Q3O-0004em-6o; Mon, 24 Apr 2017 00:32:26 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 24 Apr 2017 00:32:16 +0200 Message-Id: <20170423223216.17856-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH] target-s390x: Mask the SIGP order_code to 8bit. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Philipp Kern , Alexander Graf , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philipp Kern According to "CPU Signaling and Response", "Signal-Processor Orders", the order field is bit position 56-63. Without this, the Linux guest kernel is sometimes unable to stop emulation and enters an infinite loop of "XXX unknown sigp: 0xffffffff00000005". Signed-off-by: Philipp Kern Signed-off-by: Aurelien Jarno --- target/s390x/misc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) This patch has been sent by Philipp Kern a lot of time ago, and it seems has been lost. I am resending it, as it is still useful. diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 3bf09ea222..4946b56ab3 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -534,7 +534,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" as parameter (input). Status (output) is always R1. */ - switch (order_code) { + switch (order_code & 0xff) { case SIGP_SET_ARCH: /* switch arch */ break;