From patchwork Mon Nov 7 14:44:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 691932 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tCFdW4tFYz9t26 for ; Tue, 8 Nov 2016 01:46:55 +1100 (AEDT) Received: from localhost ([::1]:54447 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3lCE-0005yp-Rj for incoming@patchwork.ozlabs.org; Mon, 07 Nov 2016 09:46:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3lAv-0004yM-El for qemu-devel@nongnu.org; Mon, 07 Nov 2016 09:45:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c3lAq-0006kM-Ix for qemu-devel@nongnu.org; Mon, 07 Nov 2016 09:45:29 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41001) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c3lAq-0006iJ-DY for qemu-devel@nongnu.org; Mon, 07 Nov 2016 09:45:24 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.84_2 spheron) id 1c3lAn-00023L-Hq; Mon, 07 Nov 2016 15:45:21 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 1358173-5; Mon, 07 Nov 2016 14:45:21 GMT Received: from kbastian@mail.uni-paderborn.de ( [131.234.46.224]) by mail.uni-paderborn.de with SMTP id 1c3lAn-0006RQ-K2; Mon, 07 Nov 2016 14:45:21 GMT (envelope-from kbastian@mail.uni-paderborn.de) X-Envelope-From: Received: from [131.234.46.224] (helo=schnipp.uni-paderborn.de) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2 zuban) id 1c3lAn-0006RQ-K2; Mon, 07 Nov 2016 15:45:21 +0100 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Mon, 7 Nov 2016 15:44:43 +0100 Message-Id: <20161107144445.14069-4-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161107144445.14069-1-kbastian@mail.uni-paderborn.de> References: <20161107144445.14069-1-kbastian@mail.uni-paderborn.de> X-PMX-Version: 6.3.1.2588712, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2016.11.7.143618 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v2 3/5] target-tricore: Added new MOV instruction variant X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peer Adelt , rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> --- target-tricore/translate.c | 15 +++++++++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 16 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 3fec353..4fe8a5f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6034,11 +6034,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) uint32_t op2; int r3, r2, r1; + TCGv temp; + r3 = MASK_OP_RR_D(ctx->opcode); r2 = MASK_OP_RR_S2(ctx->opcode); r1 = MASK_OP_RR_S1(ctx->opcode); op2 = MASK_OP_RR_OP2(ctx->opcode); + temp = tcg_temp_new(); + switch (op2) { case OPC2_32_RR_ABS: gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); @@ -6224,6 +6228,16 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + CHECK_REG_PAIR(r3); + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -6344,6 +6358,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } + tcg_temp_free(temp); } static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index df666b0..78ba338 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1062,6 +1062,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOV_64 = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, OPC2_32_RR_OR_GE = 0x2b,