From patchwork Wed Mar 11 18:40:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin O'Connor X-Patchwork-Id: 449133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E5CD514010F for ; Thu, 12 Mar 2015 05:41:19 +1100 (AEDT) Received: from localhost ([::1]:56334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVlZG-0005zx-2w for incoming@patchwork.ozlabs.org; Wed, 11 Mar 2015 14:41:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVlYl-0005Kc-4k for qemu-devel@nongnu.org; Wed, 11 Mar 2015 14:40:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YVlYf-000811-S4 for qemu-devel@nongnu.org; Wed, 11 Mar 2015 14:40:46 -0400 Received: from mail-qc0-f176.google.com ([209.85.216.176]:46530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVlYf-00080p-OP for qemu-devel@nongnu.org; Wed, 11 Mar 2015 14:40:41 -0400 Received: by qcyl6 with SMTP id l6so12566716qcy.13 for ; Wed, 11 Mar 2015 11:40:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=CbvbaXqJBrK7MlzeeuaqyOCbedoKUDicY2VP2zZu698=; b=YYRZ/Wx869io3T9SAjcH/dajc+7JiH5q5nqky5WCRwYzLdxXS8y6O1lwLp8Cw7ZlVA SBLMip4wzSBix4n6yGho94usgK5Bn7zXmbUNJcKurBAm3bOXhI36Ux2eNQKH45LXuOKn m0H6dFLg00E6AL0aQ7eMI02eJPGGLddOY+QmY1uiII1jkT3kkrocebWHUMoH8uRsTEMD nWKnm1I6hzQdFGRCv10TbbBztXVBIQsepMJ24/Z+Sylc38sEe+e5oAd7IB8Rm6qaWW8z 0Q/aWHbEqkt8x78bxfh5JaXhzVl8IX+GdYMz8QOKnZozGPLjZNmyM3ORRPgSvWGtol6N N6ug== X-Gm-Message-State: ALoCoQnxnqNB0U959wRl8gqNnmECcCBI7u/Kpvupvb8O/e9gDJLgdRbEFuxBAdGCNq8F3D5fyMRG X-Received: by 10.140.148.201 with SMTP id 192mr22309400qhu.36.1426099241398; Wed, 11 Mar 2015 11:40:41 -0700 (PDT) Received: from localhost (207-172-170-53.c3-0.avec-ubr1.nyr-avec.ny.cable.rcn.com. [207.172.170.53]) by mx.google.com with ESMTPSA id d85sm3084938qkh.45.2015.03.11.11.40.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Mar 2015 11:40:40 -0700 (PDT) Date: Wed, 11 Mar 2015 14:40:39 -0400 From: Kevin O'Connor To: "Dr. David Alan Gilbert" Message-ID: <20150311184039.GA7341@morn.localdomain> References: <54FF4541.9080608@redhat.com> <20150310202958.GR2338@work-vm> <20150311134556.GH2334@work-vm> <20150311154220.GA26463@morn.localdomain> <20150311155306.GK2334@work-vm> <20150311163739.GA29522@morn.localdomain> <20150311165203.GL2334@work-vm> <20150311173738.GD29522@morn.localdomain> <20150311175904.GN2334@work-vm> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20150311175904.GN2334@work-vm> User-Agent: Mutt/1.5.23 (2014-03-12) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.176 Cc: Andrey Korolyov , "kvm@vger.kernel.org" , "qemu-devel@nongnu.org" , Bandan Das , kraxel@redhat.com, Paolo Bonzini Subject: Re: [Qemu-devel] E5-2620v2 - emulation stop error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Wed, Mar 11, 2015 at 05:59:04PM +0000, Dr. David Alan Gilbert wrote: > * Kevin O'Connor (kevin@koconnor.net) wrote: > > On Wed, Mar 11, 2015 at 04:52:03PM +0000, Dr. David Alan Gilbert wrote: > > > * Kevin O'Connor (kevin@koconnor.net) wrote: > > > > So, I couldn't get this to fail on my older AMD machine at all with > > > > the default SeaBIOS code. But, when I change the code with the patch > > > > below, it failed right away. > > [...] > > > > And the failed debug output looks like: > > > > > > > > SeaBIOS (version rel-1.8.0-7-gd23eba6-dirty-20150311_121819-morn.localdomain) > > > > [...] > > > > cmos_smp_count0=20 > > > > [...] > > > > cmos_smp_count=1 > > > > cmos_smp_count2=1/20 > > > > Found 1 cpu(s) max supported 20 cpu(s) > > > > > > > > I'm going to check the assembly for a compiler error, but is it > > > > possible QEMU is returning incorrect data in cmos index 0x5f? > > > > I checked the SeaBIOS assembler and it looks sane. So, I think the > > question is, why is QEMU sometimes returning a 0 instead of 127 from > > cmos 0x5f. > > My reading of the logs I've just created is that qemu doesn't think > it's ever being asked to read 5f in the failed case: > > good: > > pc_cmos_init 5f setting smp_cpus=20 > cmos: read index=0x0f val=0x00 > cmos: read index=0x34 val=0x00 > cmos: read index=0x35 val=0x3f > cmos: read index=0x38 val=0x30 > cmos: read index=0x3d val=0x12 > cmos: read index=0x38 val=0x30 > cmos: read index=0x0b val=0x02 > cmos: read index=0x0d val=0x80 > cmos: read index=0x5f val=0x13 Yeh! > cmos: read index=0x0f val=0x00 > cmos: read index=0x0f val=0x00 > cmos: read index=0x0f val=0x00 > > bad: > pc_cmos_init 5f setting smp_cpus=20 > cmos: read index=0x0f val=0x00 > cmos: read index=0x34 val=0x00 > cmos: read index=0x35 val=0x3f > cmos: read index=0x38 val=0x30 > cmos: read index=0x3d val=0x12 > cmos: read index=0x38 val=0x30 > cmos: read index=0x0b val=0x02 > cmos: read index=0x0d val=0x80 Oh! > cmos: read index=0x0f val=0x00 > cmos: read index=0x0f val=0x00 > cmos: read index=0x0f val=0x00 For what it's worth, I can't seem to trigger the problem if I move the cmos read above the SIPI/LAPIC code (see patch below). I used this command line: while true; do (sleep 5; echo -e '\001cq\n')| ../qemu/qemu-git/x86_64-softmmu/qemu-system-x86_64 -chardev file,path=foo.`date +%s`,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios -machine pc-i440fx-2.0,accel=kvm -m 1024 -smp 128 -nographic -device sga -L test 2>&1 | tee /tmp/qemu.op; grep "internal error" /tmp/qemu.op -q && break; done This is on an "AMD Phenom(tm) II X6 1090T Processor" machine. -Kevin --- a/src/fw/smp.c +++ b/src/fw/smp.c @@ -107,6 +107,8 @@ smp_setup(void) | (((u32)entry_smp - BUILD_BIOS_ADDR) << 8)); *(u64*)BUILD_AP_BOOT_ADDR = new; + u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1; + // enable local APIC u32 val = readl(APIC_SVR); writel(APIC_SVR, val | APIC_ENABLED); @@ -127,7 +129,7 @@ smp_setup(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - u8 cmos_smp_count = rtc_read(CMOS_BIOS_SMP_COUNT) + 1; + dprintf(1, "cmos_smp_count=%d\n", cmos_smp_count); while (cmos_smp_count != CountCPUs) asm volatile( // Release lock and allow other processors to use the stack. @@ -140,6 +142,8 @@ smp_setup(void) : "+m" (SMPLock), "+m" (SMPStack) : : "cc", "memory"); yield(); + dprintf(1, "cmos_smp_count2=%d/%d\n", cmos_smp_count + , rtc_read(CMOS_BIOS_SMP_COUNT) + 1); // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; diff --git a/src/post.c b/src/post.c index 9ea5620..dc11c72 100644 --- a/src/post.c +++ b/src/post.c @@ -170,6 +170,7 @@ platform_hardware_setup(void) clock_setup(); // Platform specific setup + dprintf(1, "cmos_smp_count0=%d\n", rtc_read(CMOS_BIOS_SMP_COUNT) + 1); qemu_platform_setup(); coreboot_platform_setup(); }